> -Original Message-
> From: Lyude Paul
> Sent: Tuesday, December 3, 2019 8:23 AM
> To: Lin, Wayne ; dri-de...@lists.freedesktop.org;
> amd-gfx@lists.freedesktop.org
> Cc: Kazlauskas, Nicholas ; Wentland, Harry
> ; Zuo, Jerry
> Subject: Re: [PATCH] drm/dp_mst: Correct the bug in
>
[Why]
If the payload_state is DP_PAYLOAD_DELETE_LOCAL in series, current
code doesn't delete the payload at current index and just move the
index to next one after shuffling payloads.
[How]
Drop the i++ increasing part in for loop head and decide whether
to increase the index or not according to
Since Arcturus has it own function pointer, we can move Arcturus
specific logic to there rather than leaving it entangled with
other GFX9 chips.
Change-Id: I7df7c004a0c8ac0616ded0e65144670df50f92a7
Signed-off-by: Yong Zhao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 20
Adjust the exposed function prototype so that the caller does not need
to know the MMHUB number.
Change-Id: I4420d1715984f703954f074682b075fc59e2a330
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h |
I'm, not entirely sure what this patch is trying to accomplish. I'm guessing
maybe we're leaving stale VCPI allocations from the previous topology
enablement and then somehow trying to use those again when allocating
payloads? The patch looks correct at least.
If this patch is fixing an issue,
On Mon, 2019-12-02 at 11:58 +0800, Wayne Lin wrote:
> [Why]
> If the payload_state is DP_PAYLOAD_DELETE_LOCAL in series, current
> code doesn't delete the payload at current index and just move the
> index to next one after shuffling payloads.
>
> [How]
> After shuffling payloads, decide whether
> -Original Message-
> From: amd-gfx On Behalf Of Likun
> Gao
> Sent: Monday, December 2, 2019 6:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gao, Likun ; Wang, Kevin(Yang)
> ; Feng, Kenneth
> Subject: [PATCH] drm/amdgpu/powerplay: unify smu send message function
>
> From: Likun
Series is acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Hawking Zhang
> Sent: Monday, December 2, 2019 2:04 PM
> To: amd-gfx@lists.freedesktop.org; Min, Frank ;
> Clements, John ; Deucher, Alexander
>
> Cc: Zhang, Hawking
> Subject: [PATCH 3/3] drm/amdgpu:
On Sat, Nov 30, 2019 at 10:23:31AM -0800, Linus Torvalds wrote:
> On Sat, Nov 30, 2019 at 10:03 AM Linus Torvalds
> wrote:
> >
> > I'll try to figure the code out, but my initial reaction was "yeah,
> > not in my VM".
>
> Why is it ok to sometimes do
>
> WRITE_ONCE(mni->invalidate_seq,
> -Original Message-
> From: Lyude Paul
> Sent: Tuesday, December 3, 2019 8:03 AM
> To: Lin, Wayne ; dri-de...@lists.freedesktop.org;
> amd-gfx@lists.freedesktop.org
> Cc: Kazlauskas, Nicholas ; Wentland, Harry
> ; Zuo, Jerry
> Subject: Re: [PATCH] drm/dp_mst: Remove VCPI while
> -Original Message-
> From: amd-gfx On Behalf Of Jack
> Zhang
> Sent: Monday, December 2, 2019 7:05 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jack (Jian)
> Subject: [PATCH] amd/amdgpu/sriov swSMU disable for sriov
>
> For boards greater than ARCTURUS, and under sriov
Thanks.
Reviewed-by: Alex Deucher
On Mon, Dec 2, 2019 at 9:57 PM Zhang, Hawking wrote:
>
> RE - Do we need to keep that memory around for the TAs or do they use some
> other memory?
>
> Hi Alex,
>
> Each TA owns its shared memory for the cmd that gfx send to TEE. The command
> could be
Correct the typo: gfx -> gfx driver in first sentence.
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: 2019年12月3日 10:57
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org; Min, Frank ; Clements, John
Subject: RE: [PATCH 1/3] drm/amdgpu: drop asd shared memory
RE - Do we need to keep that memory around for the TAs or do they use some
other memory?
Hi Alex,
Each TA owns its shared memory for the cmd that gfx send to TEE. The command
could be different per TA and might be using simultaneously so the shared
memory can't be shared among Tas.
Thanks Evan, I will add "{ }" before I check-in the code.
Best,
Jack
-Original Message-
From: Quan, Evan
Sent: Tuesday, December 3, 2019 10:45 AM
To: Zhang, Jack (Jian) ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian)
Subject: RE: [PATCH] amd/amdgpu/sriov swSMU disable for sriov
> -Original Message-
> From: amd-gfx On Behalf Of
> Wayne Lin
> Sent: 2019/December/01, Sunday 10:59 PM
> To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Zuo, Jerry ; Wentland, Harry
> ; Kazlauskas, Nicholas
> ; Lin, Wayne
> Subject: [PATCH] drm/dp_mst: Correct
From: Nicholas Kazlauskas
[Why]
Not having support for autoload isn't an error. If the DMUB firmware
doesn't support it then don't return DMUB_STATUS_INVALID.
[How]
Return DMUB_STATUS_OK when ->is_auto_load_done is NULL.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by:
From: Eric Yang
[Why]
DF team has produced more optimized latency numbers.
[How]
Add sr latencies to the wm table, use different latencies
for different wm sets.
Also fix bb override from registery key for these latencies.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
From: Nikola Cornij
[why]
On ASICs where number of DSCs is the same as OPPs there's no need
for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
-related issues for such platforms.
[how]
Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
as number of DSCs. This
From: Michael Strauss
[WHY]
Dali is currently being misinterpreted as Renoir,
as a result uses wrong clk mgr constructor
[HOW]
Add check to init Dali as Raven2 before it can be misidentified
Clean up & fix Raven2 & Dali ASIC checks
Signed-off-by: Michael Strauss
Reviewed-by: Eric Yang
From: Anthony Koo
[Why]
Some function pointers in the hwss function pointer table are
meant to be hw sequencer entry points to be called from dc.
However some of those function pointers are not meant to
be entry points, but instead used as a code reuse/inheritance
tool called directly by other
From: Anthony Koo
[Why]
First, to make code more consistent
Second, to get rid of those scenario where we create a second
local pointer to dc when it's already passed in.
[How]
Rename core_dc to dc
Remove duplicate local pointers to dc
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
From: Dmytro Laktyushkin
Bring this calculation in line with HW programming guide.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
From: Lucy Li
[Why]
Black screen seen after display is disabled then re-enabled.
Caused by difference in link settings when
switching between different resolutions.
[How]
In PnP case, or whenever the display is
still enabled but the driver is unloaded,
disable link before re-enabling with new
From: Nicholas Kazlauskas
[Why]
The wait for PHY init won't finish if the firmware doesn't support it.
[How]
Only hook this functionality up on DCN21 and move it out of DCN20.
For ASIC without support then this should return OK so we don't hang
while waiting in DC.
Signed-off-by: Nicholas
From: Nikola Cornij
[why]
During mode transition steer fifo could overflow. Quite often it
recovers by itself, but sometimes it doesn't.
[how]
Add steer fifo reset before unblanking the stream. Also add a short
delay when resetting dig resync fifo to make sure register writes
don't end up
From: Nicholas Kazlauskas
[Why]
On dcn21 this is programmed for tracebuffer support but isn't being
programmed on dcn20.
DMCUB execution hits an undefined address 6500 on tracebuffer
access.
[How]
Program CW5.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Leo Li
From: Paul Hsieh
[Why]
Link training failed randomly when plugging USB-C display in/out.
[How]
If link training failed, reset PHY in link re-training.
Signed-off-by: Paul Hsieh
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 32 ++---
From: Michael Strauss
[WHY]
Previous Renoir chroma viewport workaround fixed an MPO flicker by
increasing the chroma viewport size. However, when the MPO plane is
rotated 180 degrees, the viewport is read in reverse. Since the workaround
increases viewport size, when reading in reverse it causes
From: Leo Li
Summary of change:
* More DMCUB updates for Renoir
* Cleanup and refactor of DC hardware sequencer interface
Amanda Liu (1):
drm/amd/display: Fix screen tearing on vrr tests
Anthony Koo (4):
drm/amd/display: rename core_dc to dc
drm/amd/display: add separate of private hwss
From: David Galiffi
[Why]
In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
are created only on dc_construct, and next aux access will cause a panic.
[How]
Instead of calling dal_gpio_destroy_ddc, call
From: Jaehyun Chung
[Why]
Wrong guards were causing the debug option not to run.
[How]
Changed the guard to the correct one, matching the rq, ttu, dlg regs struct
members that need to be guarded. Also log a message when validation starts.
Signed-off-by: Jaehyun Chung
Reviewed-by: Alvin Lee
From: Joseph Gravenor
[why]
pstate_latency_us never gets updated from the hard coded value
in rn_clk_mgr.c
[how]
update the wm table's values before we do calculations with them
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Leo Li
---
From: Joseph Gravenor
[Why]
When video_memory_type bw_params->vram_type
is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType.
Because of this we will never report that we are using
LpDdr4MemType and never re-purpose WM set D
[How]
populate bios integrated info for renoir by adding
From: Eric Yang
[Why]
Before was using HW counter value to determine the dprefclk. Which
take into account ss, but has large variation, not good enough for
generating audio dto. Also, the bios parser code to get the ss
percentage was not working.
[How]
After this change, dprefclk is hard coded,
From: Joseph Gravenor
[Why]
new sr and pstate latencies are optimized for the case when we are not
using lpddr4 memory
[How]
have two different wm tables, one for the lpddr case and one for
non lpddr case
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Leo Li
---
From: Brandon Syu
[Why]
The variable mismatch assignment error.
[How]
To use uint32_t replace it.
Signed-off-by: Brandon Syu
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
drivers/gpu/drm/amd/display/include/i2caux_interface.h
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Joseph Gravenor
[Why]
DF team has produced more optimized latency numbers, for lpddr4
[How]
change the p-state laency in the lpddr4 wm table to the new latency
number
Signed-off-by: Joseph Gravenor
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Reza Amini
[Why]
Need support for more color management in 10bit
surface.
[How]
Provide support for DePQ for 10bit surface
Signed-off-by: Reza Amini
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
---
.../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 3 ++
From: abdoulaye berthe
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 125 +-
1 file changed, 93 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Mikita Lipski
[why]
The function is expected to return instance of the timing generator
therefore we shouldn't be returning boolean in integer function,
and we shouldn't be returning zero so changing it to -1.
Signed-off-by: Mikita Lipski
Reviewed-by: Martin Leung
Acked-by: Anthony Koo
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
From: Anthony Koo
[Why]
We want to know DP protocol version
[How]
In DC create we initialize a cap to indicate the max
DP protocol version supported
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
From: Hugo Hu
[Why]
The link setting will be modify after disable phy
and due to DP Compliance Fails.
[How]
Save and resotre link setting for disable link phy when link retraining.
Signed-off-by: Hugo Hu
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
From: "Leo (Hanghong) Ma"
[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.
[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173
> -Original Message-
> From: amd-gfx On Behalf Of
> Emily Deng
> Sent: 2019/November/30, Saturday 5:42 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily
> Subject: [PATCH] drm/amdgpu/sriov: No need the event 3 and 4 now
>
> As will call unload kms when initialize fail, and the
> -Original Message-
> From: Hawking Zhang
> Sent: Monday, December 2, 2019 1:04 AM
> To: amd-gfx@lists.freedesktop.org; Min, Frank ;
> Clements, John ; Deucher, Alexander
>
> Cc: Zhang, Hawking
> Subject: [PATCH 3/3] drm/amdgpu: load np fw prior before loading the TAs
>
> Platform TAs
> -Original Message-
> From: Hawking Zhang
> Sent: Monday, December 2, 2019 1:04 AM
> To: amd-gfx@lists.freedesktop.org; Min, Frank ;
> Clements, John ; Deucher, Alexander
>
> Cc: Zhang, Hawking
> Subject: [PATCH 2/3] drm/amdgpu: unload asd in psp hw de-init phase
>
> issue
Reviewed-by: Anthony Koo
-Original Message-
From: Stanley.Yang
Sent: Thursday, November 28, 2019 10:52 PM
To: amd-gfx-boun...@lists.freedesktop.org
Cc: Koo, Anthony ; Yang, Stanley
Subject: [PATCH] drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs
struct
In dcn20_funcs and
From: abdoulaye berthe
[Why]
When setting lttpr mode, the new mode to bet is not logged properly.
[How]
Update log message to show the right mode.
Signed-off-by: abdoulaye berthe
Reviewed-by: George Shen
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
1 file
From: Nicholas Kazlauskas
[Why]
Scratch registers are limited on the DMCUB and we have an expanding
list of state to track between driver and DMCUB.
[How]
Place shared state in cache window 6. The cache window size is aligned
to the size of the cache line on the DMCUB to make it easy to
From: Aric Cyr
[Why]
Cursor position needs to take into account plane scaling as well.
[How]
Translate cursor coords from stream space to plane space.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Leo Li
Acked-by: Nicholas Kazlauskas
---
From: Reza Amini
[Why]
Need support for more color management in 10bit
surface.
[How]
Provide support for DePQ for 10bit surface
Signed-off-by: Reza Amini
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 3 +++
From: Nicholas Kazlauskas
[Why]
Commands will be considered a stable ABI between driver and firmware.
Commands are also split between DC commands, DAL feature commands,
and VBIOS commands.
Commands are currently not designated to a specific ID and the enum
does not provide a stable ABI.
We
From: Wenjing Liu
[why]
add_dsc_to_stream_resource could be called for validation.
Failing validation is completely fine.
However failing it inside commit streams is bad.
This code could be triggered for both contexts.
The function itself cannot distinguish the caller, which
makes it impossible
From: Noah Abradjian
[Why]
MPCC programming was being missed during certain split pipe enables due
to full_update flag not being true. This caused a momentary flash on
half the screen. After discussion, determined we should not have that
flag check within update_mpcc, as it should always perform
From: Wenjing Liu
dc needs to expose its internal dsc policy.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 14 ++-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 103
2 files changed, 75
From: Yongqiang Sun
[Why]
It seems always request passive flip on RN due to incorrect compare
clock state to determine optization.
[How]
Instead of calling memcmp, compare clock state member to determine the
condition.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
From: Amanda Liu
[Why]
Screen tearing is present in tests when setting the frame rate to
certain fps
[How]
Revert previous optimizations for low frame rates.
Signed-off-by: Amanda Liu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
.../amd/display/modules/freesync/freesync.c | 32
From: Nicholas Kazlauskas
[Why]
To quickly validate whether DMCUB is running and accepting commands for
offload testing we want to intercept a common sequence as part of
modeset programming.
[How]
OTG enable will cause the most impact in terms of golden register
changes and it's a single
From: Eric Yang
Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Dmytro Laktyushkin
In preparation for further changes
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 3 +++
From: abdoulaye berthe
[Why]
When training with repeater the aux read interval must be set to
repeater specific aux_red_interval. This value is always 100us for CR.
[How]
Check for repeater when setting the aux_rd_interval in channel
equalization.
Use the right offset in the aux_rd_interval
From: Krunoslav Kovac
[Why]
Currently we require HDR_MULT >= 1.0
There are scenarios where we need < 1.0
[How]
Only guard against 0 - it will black-screen image.
It is up to higher-level logic to decide what HDR_MULT
values are allowed in each particular case.
Signed-off-by: Krunoslav Kovac
From: George Shen
[Why]
When a timeout occurs after a DEFER, some devices require more retries
than in the case of a regular timeout.
[How]
In a timeout occurrence, check whether a DEFER has occurred before the
timeout and retry MAX_DEFER_RETRIES retries times instead of
MAX_TIMEOUT_RETRIES.
From: Noah Abradjian
[Why]
I was advised that we may need to check for mpcc idle in more cases
than just when opp_changed is true. Also, mpcc_inst is equal to
pipe_idx, so remove for loop.
[How]
Remove opp_changed flag check and mpcc_inst loop.
Signed-off-by: Noah Abradjian
Reviewed-by:
From: Joseph Gravenor
[Why]
DF team has produced more optimized sr latency numbers, for lpddr4
[How]
change the sr laency in the lpddr4 wm table to the new latency
number
Signed-off-by: Joseph Gravenor
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Anthony Koo
[Why]
It is causing green Line at the bottom of SDR 480p
MPO playback
[How]
Limit workaround to vertical > 512
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 2 +-
1 file changed, 1 insertion(+),
From: Wenjing Liu
[why]
Need to support 6 bpp for 420 pixel encoding only.
[how]
Add a dc function to determine what bpp range can be supported
for given pixel encoding.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h |
From: Noah Abradjian
[Why]
I was advised that we don't need this call of program_front_end, as
earlier and later calls in the same sequence are sufficient.
[How]
Remove first call of program_front_end in dc_commit_state_no_check.
Signed-off-by: Noah Abradjian
Reviewed-by: Yongqiang Sun
>
> Most likely not. There is support for resizing the VRAM BAR, but usually
> you can only make it larger and not smaller.
> Please give me the output of "sudo setpci -s 0001:01:00.0 ECAP15+4.l
> ECAP15+8.l" if you want to double check that.
>
Okay I'll try it tomorrow. What does the " sudo
> -Original Message-
> From: Hawking Zhang
> Sent: Monday, December 2, 2019 1:04 AM
> To: amd-gfx@lists.freedesktop.org; Min, Frank ;
> Clements, John ; Deucher, Alexander
>
> Cc: Zhang, Hawking
> Subject: [PATCH 1/3] drm/amdgpu: drop asd shared memory
>
> asd shared memory is not
On Wed, 27 Nov 2019 at 18:37, Daniel Vetter wrote:
>
> On Wed, Nov 27, 2019 at 06:32:56PM +, Emil Velikov wrote:
> > On Wed, 27 Nov 2019 at 18:04, Daniel Vetter wrote:
> > >
> > > On Wed, Nov 27, 2019 at 04:27:29PM +, Emil Velikov wrote:
> > > > On Wed, 27 Nov 2019 at 07:41, Boris
On Mon, Dec 2, 2019 at 1:11 AM Changfeng.Zhu wrote:
>
> From: changzhu
>
> It may cause timeout waiting for sem acquire in VM flush when using
> invalidate semaphore for picasso. So it needs to avoid using invalidate
> semaphore for piasso.
Is this really just picasso? I think it would be
DP 1.4 edid corruption test requires source DUT to write calculated
CRC, not the corrupted CRC from reference sink.
Return the calculated CRC back, and initiate the required sequence.
-v2: Have separate routine for returning real CRC
-v3: Rewrite checksum computation routine to avoid duplicated
-v3: Rename to avoid confusion
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Harry Wentland
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 35 +-
1 file changed, 7 insertions(+), 28 deletions(-)
diff --git
Unlike DP 1.2 Compliance test 4.2.2.6, DP 1.4 requires to calculate real
CRC value of the last edid data block, and write it back.
Current edid CRC calculate routine adds the last CRC byte, and check if
non-zero or not. Need to return the actual CRC value when corruption is
detected.
[For CI]
On Fri, Nov 29, 2019 at 01:00:36AM -0500, Kenny Ho wrote:
> On Tue, Oct 1, 2019 at 10:31 AM Michal Koutný wrote:
> > On Thu, Aug 29, 2019 at 02:05:19AM -0400, Kenny Ho wrote:
> > > +struct cgroup_subsys drm_cgrp_subsys = {
> > > + .css_alloc = drmcg_css_alloc,
> > > + .css_free
From: Likun Gao
Drop smu_send_smc_msg function from ASIC specify structure.
Reuse smu_send_smc_msg_with_param function for smu_send_smc_msg.
Set paramer to 0 for smu_send_msg function, otherwise it will send
with previous paramer value (Not a certain value).
Signed-off-by: Likun Gao
---
Hi, Team,
Would you please help to review this patch?
Best,
Jack
-Original Message-
From: Jack Zhang
Sent: Monday, December 2, 2019 7:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian)
Subject: [PATCH] amd/amdgpu/sriov swSMU disable for sriov
For boards greater than
Am 02.12.19 um 15:43 schrieb Nirmoy:
On 11/29/19 7:42 PM, Christian König wrote:
Am 29.11.19 um 15:29 schrieb Nirmoy:
Hi Christian,
On 11/26/19 10:45 AM, Christian König wrote:
It looks like a start, but there numerous things which needs to be
fixed.
Question number one is: What's that
Hi Yusuf,
Am 02.12.19 um 15:20 schrieb Yusuf Altıparmak:
That is an expected result. 256MB is not enough for the VRAM BAR
and the doorbell BAR to fit into. But you can still use VGA
emulation that way if I'm not completely mistaken.
Hmm, then what procedure should I follow to
[AMD Official Use Only - Internal Distribution Only]
From: Gao, Likun
Sent: Monday, December 2, 2019 6:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Kevin(Yang) ; Feng, Kenneth
; Gao, Likun
Subject: [PATCH] drm/amdgpu/powerplay: unify smu send message
Hi Yusuf,
Am 02.12.19 um 12:41 schrieb Yusuf Altıparmak:
My embedded board is freezing when I put E9171 on PCIe. What is the
meaning of Unrecoverable Machine Check error about GPU?
Well see the explanation on Wikipedia for example:
https://en.wikipedia.org/wiki/Machine-check_exception
In
>
>
> I attached my dts file.
>
> System is working fine when GPU is not plugged in.
>
> *This is the last console log before freeze:*
> [drm] amdgpu kernel modesetting enabled.
>
> [drm] initializing kernel modesetting (POLARIS12 0x1002:0x6987
> 0x1787:0x2389 0x80).
> [drm] register mmio base:
For boards greater than ARCTURUS, and under sriov platform,
swSMU is not supported because smu ip block is commented at
guest driver.
Generally for sriov, initialization of smu is moved to host driver.
Thus, smu sw_init and hw_init will not be executed at guest driver.
Without sw structure being
My embedded board is freezing when I put E9171 on PCIe. What is the meaning
of Unrecoverable Machine Check error about GPU?
Could PCIe settings in .dts file cause this problem? If it is, is there any
sample PCIe configuration for E9171? I attached my dts file.
System is working fine when GPU is
[AMD Official Use Only - Internal Distribution Only]
From: Grodzovsky, Andrey
Sent: Saturday, November 30, 2019 12:22 AM
To: Ma, Le ; amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhou1, Tao ;
Deucher, Alexander ; Li, Dennis ;
Zhang, Hawking
Subject: Re: [PATCH 07/10] drm/amdgpu: add
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kevin Wang
But it's better to optimize the flow of control in is_support_sw_smu()
Best Regards,
Kevin
From: amd-gfx on behalf of Jack Zhang
Sent: Monday, December 2, 2019 7:05 PM
To:
On 11/29/19 7:42 PM, Christian König wrote:
Am 29.11.19 um 15:29 schrieb Nirmoy:
Hi Christian,
On 11/26/19 10:45 AM, Christian König wrote:
It looks like a start, but there numerous things which needs to be
fixed.
Question number one is: What's that good for? Entities are not the
problem
Hi Yusuf,
At first, I am using NXP T1042D4RDB-64B which has 256 MB PCIe buffer
according to its. PCIe memory range was arranged to 256 MB in .dts
file and in U-boot configuration file. Driver was giving error with
exit code -12 (OUT_OF_MEMORY). But I was able to reach the linux console.
> That is an expected result. 256MB is not enough for the VRAM BAR and the
> doorbell BAR to fit into. But you can still use VGA emulation that way if
> I'm not completely mistaken.
>
Hmm, then what procedure should I follow to take a VGA output. It seems
Graphic Card does not have a VGA output.
Applied. thanks!
Alex
On Wed, Nov 27, 2019 at 11:51 AM Harry Wentland wrote:
>
> On 2019-11-20 12:22 p.m., Colin King wrote:
> > From: Colin Ian King
> >
> > The msg_id field is being assigned twice. Fix this by replacing the second
> > assignment with an assignment to msg_size.
> >
> >
Applied the series. Thanks!
Alex
On Wed, Nov 27, 2019 at 12:42 PM zhengbin wrote:
>
> zhengbin (5):
> drm/amd/powerplay: Remove unneeded variable 'result' in smu10_hwmgr.c
> drm/amd/powerplay: Remove unneeded variable 'result' in vega10_hwmgr.c
> drm/amd/powerplay: Remove unneeded
Applied the series. Thanks!
Alex
On Thu, Nov 28, 2019 at 9:46 AM Harry Wentland wrote:
>
> Series is
> Reviewed-by: Harry Wentland
>
> Harry
>
> On 2019-11-27 9:31 p.m., zhengbin wrote:
> > zhengbin (4):
> > drm/amd/display: Remove unneeded semicolon in bios_parser.c
> > drm/amd/display:
On Thu, Nov 28, 2019 at 6:47 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> The same workaround is used for gfx7.
> Both PAL and Mesa use it for gfx8 too, so port this commit to
> gfx_v8_0_ring_emit_fence_gfx.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer
Reviewed-by: Alex Deucher
> ---
>
Applied. thanks!
Alex
On Mon, Dec 2, 2019 at 10:47 AM Colin King wrote:
>
> From: Colin Ian King
>
> The variable v_total is being initialized with a value that is never
> read and it is being updated later with a new value. The initialization
> is redundant and can be removed.
>
>
For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
"interesting" modes would be disabled, leaving only low-res or low
framerate modes.
This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
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