[AMD Public Use]
I think the real reason is we have " *hw_supported &= AMDGPU_RAS_BLOCK_MASK;"
already, but the patch is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2020年6月2日 13:58
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao ; Li,
>
[AMD Public Use]
Exactly Tao.
When hw_support capability is aligned with AMDGPU_RAS_BLOCK_MASK by and
operation, sw_support capability is calculated on top of hw_support value and
amdgpu_ras_mask accordingly.
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Tuesday, June 2,
[AMD Public Use]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2020年6月2日 13:50
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao
> Cc: Chen, Guchun
> Subject: [PATCH] drm/amdgpu: fix RAS memory leak in error case
>
> RAS context memory
From: Likun Gao
move smu_v11_0_get_max_power_limit and smu_v11_0_set_thermal_range
function from smu_v11_0.c to asic specific _ppt.c to avoid powerplay
table conflict with different ASIC with smu11.
Signed-off-by: Likun Gao
Change-Id: I194f44e9f59daf19fa4758ed746fa13ccece4308
---
On Tue, Jun 2, 2020 at 10:35 AM Andy Shevchenko
wrote:
>
> On Tue, Jun 2, 2020 at 5:21 PM Alex Deucher wrote:
> > On Tue, Jun 2, 2020 at 10:00 AM Andy Shevchenko
> > wrote:
> > > On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J
> > > wrote:
> > > > >From: dri-devel On Behalf Of
> > > > >Piotr
On Mon, Jun 1, 2020 at 3:31 AM Evan Quan wrote:
>
> To avoid possible memory leak.
>
> Change-Id: I4740eac7fc2c6e934ec8f503e5a98057f0902f4a
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
>
On Mon, Jun 1, 2020 at 3:31 AM Evan Quan wrote:
>
> Since the structure comes with only several bytes.
>
> Change-Id: Ie9df0db543fdd4cf5b963a286ef40dee03c436bf
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ---
>
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Kevin Wang
Best Regards,
Kevin
From: Gao, Likun
Sent: Tuesday, June 2, 2020 5:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Gao, Likun
Subject:
Change-Id: Ic010440ef625f6f29e91f267a6f284f9b6554e1f
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b6331712..fcbd875
[AMD Official Use Only - Internal Distribution Only]
>-Original Message-
>From: Emily Deng
>Sent: Tuesday, June 2, 2020 7:54 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] drm/amdgpu/sriov: Disable pm for multiple vf sriov
>
>Change-Id:
On Tue, Jun 2, 2020 at 9:56 AM Liang, Prike wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ah not aware the enable patch before. But the already enable patch seems
> can't fallback to legacy gpuinfo FW load method when not support discovery
> and also may miss destroy the
On Tue, Jun 2, 2020 at 5:21 PM Alex Deucher wrote:
> On Tue, Jun 2, 2020 at 10:00 AM Andy Shevchenko
> wrote:
> > On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J
> > wrote:
> > > >From: dri-devel On Behalf Of
> > > >Piotr Stankiewicz
> > > > int nvec =
On Mon, Jun 1, 2020 at 3:31 AM Evan Quan wrote:
>
> Postpone some operations which are not must for hw setup to
> late_init. Thus, code sharing is possible between hw_init/fini and
> suspend/resume. Also this makes code more clean and readable.
>
> Change-Id:
On Tue, Jun 2, 2020 at 8:53 AM Kent Russell wrote:
>
> Add support for unique_id and serial_number, as these are now
> the same value, and will be for future ASICs as well.
>
> v2: Explicitly create unique_id only for VG10/20/ARC
>
> Signed-off-by: Kent Russell
> Change-Id:
On Mon, Jun 1, 2020 at 3:30 AM Evan Quan wrote:
>
> To make code more clean and readable by moving ASIC
> specific code to its own file, more code sharing and
> dropping unused code.
There seem to be multiple things going on here. It's kind of hard to
follow all of the changes. Maybe split
On Mon, Jun 1, 2020 at 3:31 AM Evan Quan wrote:
>
> Combine and simplify the logics for setup pptable.
>
> Change-Id: I062f15eab586050593afd960432c4c70fbdd5d41
> Signed-off-by: Evan Quan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 17
>
[AMD Public Use]
> -Original Message-
> From: Alex Deucher
> Sent: Tuesday, June 2, 2020 10:45 AM
> To: Russell, Kent
> Cc: amd-gfx list
> Subject: Re: [PATCH 2/2] drm/amdgpu: Add unique_id and serial_number for
> Arcturus v2
>
> On Tue, Jun 2, 2020 at 8:53 AM Kent Russell wrote:
>
On Tue, Jun 2, 2020 at 10:00 AM Andy Shevchenko
wrote:
>
> On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J
> wrote:
> > >-Original Message-
> > >From: dri-devel On Behalf Of
> > >Piotr Stankiewicz
> > >Sent: Tuesday, June 2, 2020 5:21 AM
> > >To: Alex Deucher ; Christian König
> > >;
On Mon, Jun 1, 2020 at 10:08 AM Huang Rui wrote:
>
> Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it.
>
> Signed-off-by: Huang Rui
> Reviewed-by: Kevin Wang
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16
>
On Mon, Jun 1, 2020 at 3:30 AM Evan Quan wrote:
>
> Combine and simplify the logics for retrieving bootup
> clocks.
>
> Change-Id: Ifca28c454f3769dece0cc705ba054ff34db0ab60
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 4 -
>
On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Piotr Stankiewicz
> >Sent: Tuesday, June 2, 2020 5:21 AM
> >To: Alex Deucher ; Christian König
> >; David Zhou ; David
> >Airlie ; Daniel Vetter
> >Cc: Stankiewicz, Piotr ;
On Mon, Jun 1, 2020 at 3:30 AM Evan Quan wrote:
>
> These APIs internally guard they will not break ARCTURUS.
>
> Change-Id: Ib6775c1c8c5211ea45db6c3fb604a8279411ab37
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 38
On Mon, Jun 1, 2020 at 3:31 AM Evan Quan wrote:
>
> Eliminate the buffer allocation and drop the unnecessary
> overdrive table uploading.
>
> Change-Id: I8ba5383a330e6d5355cea219147500c1b4a43f47
> Signed-off-by: Evan Quan
Acked-by: Alex Deucher
> ---
>
[AMD Official Use Only - Internal Distribution Only]
Ah not aware the enable patch before. But the already enable patch seems can't
fallback to legacy gpuinfo FW load method when not support discovery and also
may miss destroy the discovery_bin object when driver shut down.
Thanks,
Prike
>
On Mon, Jun 1, 2020 at 3:30 AM Evan Quan wrote:
>
> To fit common design. And this can simplify the buffer deallocation.
>
> Change-Id: Iee682e76aadb5f34861d69d5794ced44f0a78789
> Signed-off-by: Evan Quan
Took me a little while to sort out the functional changes from the
non-functional moves.
Add support for unique_id and serial_number, as these are now
the same value, and will be for future ASICs as well.
v2: Explicitly create unique_id only for VG10/20/ARC
v3: Change set_unique_id to get_unique_id for clarity
Signed-off-by: Kent Russell
Change-Id:
Add the ReadSerial definitions for Arcturus to the arcturus_ppsmc.h
header for use with unique_id
Unrevert: Supported in SMU 54.23, update values to match SMU spec
Signed-off-by: Kent Russell
Reviewed-by: Alex Deucher
Change-Id: I9a70368ea65b898b3c26f0d57dc088f21dab9c53
---
Seeing as there is shorthand available to use when asking for any type
of interrupt, or any type of message signalled interrupt, leverage it.
Signed-off-by: Piotr Stankiewicz
Reviewed-by: Andy Shevchenko
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 8
1 file changed, 4 insertions(+),
On Tue, Jun 2, 2020 at 12:58 PM Stankiewicz, Piotr
wrote:
> > -Original Message-
> > From: Andy Shevchenko
> > Sent: Tuesday, June 2, 2020 11:49 AM
> > To: Stankiewicz, Piotr
> > Cc: Alex Deucher ; Christian König
> > ; David Zhou ; David
> > Airlie ; Daniel Vetter ; amd-
> >
[AMD Official Use Only - Internal Distribution Only]
Hi Emily,
How about to move it into smu_hw_init()?
Best Regards,
Frank
-邮件原件-
发件人: Deng, Emily
发送时间: 2020年6月2日 20:08
收件人: Deng, Emily ; amd-gfx@lists.freedesktop.org
抄送: Min, Frank
主题: RE: [PATCH] drm/amdgpu/sriov: Disable pm for
Am 01.06.20 um 20:00 schrieb Alex Deucher:
From: Jack Xiao
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.
Signed-off-by: Jack Xiao
Acked-by: Alex Deucher
Reviewed-by: Hawking Zhang
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
Op 12-05-2020 om 11:08 schreef Christian König:
> Am 12.05.20 um 10:59 schrieb Daniel Vetter:
>> But only for non-zero timeout, to avoid false positives.
>>
>> One question here is whether the might_sleep should be unconditional,
>> or only for real timeouts. I'm not sure, so went with the more
>>
Am 01.06.20 um 20:00 schrieb Alex Deucher:
From: Jack Xiao
Implement mes ring functions and set up them.
Signed-off-by: Jack Xiao
Acked-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 43 ++
1
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5294aa7..8ed6c90 100644
---
On Mon, Jun 1, 2020 at 10:14 PM Liang, Prike wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ping...
Already enabled:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=amd-staging-drm-next=e467ab869f5783cf93d4cf24c6ac647cc29d1fb5
Alex
>
> Thanks,
> > -Original
>-Original Message-
>From: dri-devel On Behalf Of
>Piotr Stankiewicz
>Sent: Tuesday, June 2, 2020 5:21 AM
>To: Alex Deucher ; Christian König
>; David Zhou ; David
>Airlie ; Daniel Vetter
>Cc: Stankiewicz, Piotr ; dri-
>de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; linux-
Add the ReadSerial definitions for Arcturus to the arcturus_ppsmc.h
header for use with unique_id
Unrevert: Supported in SMU 54.23, update values to match SMU spec
Signed-off-by: Kent Russell
Reviewed-by: Alex Deucher
Change-Id: I9a70368ea65b898b3c26f0d57dc088f21dab9c53
---
> -Original Message-
> From: Andy Shevchenko
> Sent: Tuesday, June 2, 2020 11:49 AM
> To: Stankiewicz, Piotr
> Cc: Alex Deucher ; Christian König
> ; David Zhou ; David
> Airlie ; Daniel Vetter ; amd-
> g...@lists.freedesktop.org; dri-devel ; Linux
> Kernel Mailing List
> Subject: Re:
The primary objective of this patch series is to change the behaviour
of pci_alloc_irq_vectors_affinity such that it forwards the MSI-X enable
error code when appropriate. In the process, though, it was pointed out
that there are multiple places in the kernel which check/ask for message
signalled
On Tue, Jun 2, 2020 at 12:24 PM Piotr Stankiewicz
wrote:
>
> Seeing as there is shorthand available to use when asking for any type
> of interrupt, or any type of message signalled interrupt, leverage it.
>
> Signed-off-by: Piotr Stankiewicz
> Reviewed-by: Andy Shevchenko
> ---
>
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Gao, Likun
Sent: Tuesday, June 2, 2020 5:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Gao, Likun
Subject: [PATCH] drm/amd/powerplay: move powerplay table
Am 01.06.20 um 20:19 schrieb Alex Deucher:
From: Likun Gao
Each of HDP flush engine should be used by one ring, correct allocate of
hdp flush engine to SDMA ring.
Correct me value of each SDMA ring, as it was cleared when init microcode.
Signed-off-by: Likun Gao
Signed-off-by: Alex Deucher
Add support for unique_id and serial_number, as these are now
the same value, and will be for future ASICs as well.
v2: Explicitly create unique_id only for VG10/20/ARC
Signed-off-by: Kent Russell
Change-Id: I3b036a38b19cd84025399b0706b2dad9b7aff713
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
On Tue, Jun 2, 2020 at 5:30 AM Christian König wrote:
>
> Am 01.06.20 um 20:00 schrieb Alex Deucher:
> > From: Jack Xiao
> >
> > As mes ring directly submits to hardwared,
> > it's no need to set up GPU scheduler for mes ring.
> >
> > Signed-off-by: Jack Xiao
> > Acked-by: Alex Deucher
> >
On Tue, Jun 2, 2020 at 6:00 AM Christian König
wrote:
>
> Am 01.06.20 um 20:00 schrieb Alex Deucher:
> > From: Jack Xiao
> >
> > Implement mes ring functions and set up them.
> >
> > Signed-off-by: Jack Xiao
> > Acked-by: Alex Deucher
> > Reviewed-by: Hawking Zhang
> > Signed-off-by: Alex
On Tue, Jun 2, 2020 at 12:22 PM Kent Russell wrote:
>
> Add support for unique_id and serial_number, as these are now
> the same value, and will be for future ASICs as well.
>
> v2: Explicitly create unique_id only for VG10/20/ARC
> v3: Change set_unique_id to get_unique_id for clarity
>
>
Rather than checking the ring type manually. We already set
this for MES and KIQ (and a few other special cases).
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
This reverts commit 4dea25853a6c0c16e373665153bd9eb6edc6319e.
This changes structs used by the hardware and breaks dpm on some cards.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/sislands_smc.h | 2 +-
Have strict check on bo mapping since on some systems, such as A+A or
hybrid, the cpu might support 5 level paging or can address memory above
48 bits but gpu might be limited by hardware to just use 48 bits. In
general, this applies to all asics where this limitation can be checked
against their
On Tue, Jun 02, 2020 at 11:16:17AM +0200, Piotr Stankiewicz wrote:
> The primary objective of this patch series is to change the behaviour
> of pci_alloc_irq_vectors_affinity such that it forwards the MSI-X enable
> error code when appropriate. In the process, though, it was pointed out
> that
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML parameters before committing to the hardware.
[How]
If the update type is FULL then call
From: Hersen Wu
dp/hdmi ati hda is not shown in audio settings
Signed-off-by: Hersen Wu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
sound/pci/hda/hda_intel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index
On 6/2/2020 3:51 PM, Christian König wrote:
Hi Rajneesh,
I think we have reviewed the patch multiple times now, you can push it
to the amd-staging-drm-next branch.
Thanks Christian. Just wanted to make sure its sent once on the public
list. I'll push it to the branch now.
Regards,
We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation. Check both to determine
the proper blanked state.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
On 2020-06-01 3:30 a.m., Evan Quan wrote:
> Since the structure comes with only several bytes.
>
This is not a good commit message as it doesn't describe
what is being done. It evokes the "Yes? Then what?" questions
from a reader.
Perhaps a better one would be:
Allocate the struct
On 2020-06-02 5:25 p.m., Alex Deucher wrote:
We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation. Check both to determine
the proper blanked state.
Bug:
Hi Rajneesh,
I think we have reviewed the patch multiple times now, you can push it
to the amd-staging-drm-next branch.
Regards,
Christian.
Am 02.06.20 um 20:27 schrieb Rajneesh Bhardwaj:
Have strict check on bo mapping since on some systems, such as A+A or
hybrid, the cpu might support 5
From: "Tianci.Yin"
The bounding box is still needed by Navi12, temporarily read it from gpu_info
firmware. Should be droped when DAL no longer needs it.
Change-Id: Ifc330ec860f9b0665134a81df2fc80ca91c41a33
Reviewed-by: Alex Deucher
Reviewed-by: Xiaojie Yuan
Signed-off-by: Tianci.Yin
---
From: Likun Gao
Update sienna_cichlid driver if header file to match pptable changes.
Signed-off-by: Likun Gao
Change-Id: Ie0652935d512124c03f16ae75c44e134567ef5da
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 ++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2
As IO operations(access to SMU internals) and possible sleep are
involved in throttling logging. Workqueue can handle them well.
Otherwise we may hit "scheduling while atomic" error.
Change-Id: I454d593e965e54b13fdf04c112abb0a022204278
Signed-off-by: Evan Quan
---
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Wednesday, June 3, 2020 12:36 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Gao,
Likun
Subject: [PATCH]
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: Wednesday, June 3, 2020 10:08 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Xu, Feifei
; Yuan, Xiaojie ; Li, Pauline
; Yin, Tianci (Rico)
Subject:
[AMD Official Use Only - Internal Distribution Only]
Thanks Frank, already sent out the modified patch, please help review again.
Best wishes
Emily Deng
>-Original Message-
>From: Min, Frank
>Sent: Tuesday, June 2, 2020 8:34 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
63 matches
Mail list logo
