Hi Johannes,
The s3 resume issue looks to be a problem with amdgpu/display. Could you
give the attached patch a try?
Thanks,
Leo
On 2017-11-23 07:27 AM, Johannes Hirte wrote:
On 2017 Nov 23, Chunming Zhou wrote:
See the attached email, they fixed same issue, each of them is ok to fix
your
On 2017-11-23 02:52 PM, Harry Wentland wrote:
Signed-off-by: Harry Wentland
Reviewed-by: Leo (Sunpeng) Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
2 files changed, 4 insertions(+)
On 2017-11-17 11:46 PM, Andrey Grodzovsky wrote:
On 2017-11-16 10:32 AM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li"
Within atomic check, dm_update_crtcs_state is called twice. First to
remove from the dc_state, and subsequently to add to it.
In both calls, a
On 2017-11-10 01:40 PM, Andrey Grodzovsky wrote:
On 11/10/2017 01:38 PM, Andrey Grodzovsky wrote:
On 11/09/2017 03:05 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li"
This is a followup to the following revert:
Rex Zhu Revert "drm/amd/display: Match actual
On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
On 11/09/2017 03:05 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li"
When disabling pipe splitting, we need to make sure we disable both
planes used.
This should be done for Linux as well.
Change-Id:
Ping :)
Leo
On 2018-05-03 02:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This patchset ended up looking quite different from the first. To address some
fundamental issues, the design had to be reworked.
Things gathered from previous review:
1. User client
On 2018-05-18 04:01 AM, Michel Dänzer wrote:
On 2018-05-17 11:44 PM, Leo Li wrote:
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This will persist color management properties
On 2018-05-18 06:33 AM, Michel Dänzer wrote:
From: Michel Dänzer
Leo pointed out that drmmode_do_crtc_dpms wasn't getting called when
turning off an output with
xrandr --output --off
This meant that the vblank sequence number and timestamp wouldn't be
saved
On 2018-05-18 04:10 AM, Michel Dänzer wrote:
On 2018-05-17 11:43 PM, Leo Li wrote:
On 2018-05-16 01:06 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
3. The three color management properties (Degamma LUT, Color
Transform Matrix
(CTM), and Gamma LUT
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This will persist color management properties on a CRTC across DPMS
state changes.
Signed-off-by: Leo (Sunpeng) Li
---
On 2018-05-16 01:06 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
3. The three color management properties (Degamma LUT, Color Transform Matrix
(CTM), and Gamma LUT) are hard-coded into the DDX driver, to be listed (as
disabled) regardless of whether a
On 2018-05-16 01:08 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
Push staged values on the driver-private CRTC, to kernel DRM when it's
initialized. This is to flush out any previous state that hardware was
in, and
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
The properties on an RandR output needs to stay consistent throughout
it's lifecycle. However, we cannot list color properties on an output if
there is
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
The dpms_mode flag on the driver-private CRTC was not being set when
it's DPMS state is set to off. This causes some problems when toggling
it back on,
On 2018-05-16 01:07 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
Non-legacy color management consists of 3 properties on the CRTC:
Degamma LUT, Color Transformation Matrix (CTM), and Gamma LUT.
Add these properties
On 2018-06-14 12:57 PM, Michel Dänzer wrote:
Hi Leo,
sorry for the delay.
Appreciate the review, it's not a small change by any means :)
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new
On 2018-06-06 01:03 PM, Michel Dänzer wrote:
On 2018-06-06 06:01 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new patchset. Per
Michel's suggestions, there have been various
On 2018-05-28 11:20 AM, Michel Dänzer wrote:
On 2018-05-28 05:06 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
For cases where the CRTC is inactive (DPMS off), where a modeset is not
required, yet the CRTC is still in the atomic state, we should not
attempt to
On 2018-06-06 01:03 PM, Michel Dänzer wrote:
On 2018-06-06 06:01 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new patchset. Per
Michel's suggestions, there have been various
On 2018-05-28 05:15 AM, Michel Dänzer wrote:
Hi Leo,
commit e277adc5a06c "drm/amd/display: Hookup color management functions"
broke suspend to RAM on my development system with a Tonga and a Turks
(using the radeon driver). It sometimes, but not always happens when
trying to suspend from
On 2018-07-31 02:24 PM, Dan Carpenter wrote:
[ Potential security issue, if I'm reading the code correctly. I don't
really know the code and I haven't looked at the larger context. -dan ]
Hello Leo (Sunpeng) Li,
The patch edf6ffe4f47e: "drm/amd/display: Read AUX channel even if
only
On 2018-08-17 03:16 AM, Christian König wrote:
Am 16.08.2018 um 21:44 schrieb sunpeng...@amd.com:
[SNIP]
+config DRM_AMD_DC_DCN1_0
+ bool "DCN 1.0 Raven family"
+ depends on DRM_AMD_DC && X86
+ default y
+ help
+ Choose this option if you want to have
+ RV family for
On 2018-07-19 11:17 AM, Harry Wentland wrote:
On 2018-07-19 10:36 AM, Christian König wrote:
Note that Harry and Leo Li are maintainers for that stuff.
Signed-off-by: Christian König
Reviewed-by: Harry Wentland
Reviewed-by: Leo Li
Harry
---
MAINTAINERS | 8
1 file
On 2018-02-27 05:34 AM, Michel Dänzer wrote:
On 2018-02-26 09:15 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li"
Non-legacy LUT size should reflect hw capability. Change size from 256
to 4096.
However, X doesn't seem to play with legacy LUTs of such size.
Therefore,
On 2018-04-04 11:17 AM, Deucher, Alexander wrote:
Do other DCE blocks need this fix as well? Or is this code shared with
say DCE8 and DCE10?
Yes, it's all shared. The hook for this is initialized in
dce110_hw_sequencer_construct(), which is called for all DCE.
Leo
Alex
On 2018-04-09 01:36 PM, Tom St Denis wrote:
This commit
commit 5fadc6fe773862f59f8a54480f06f097f0719c26
Author: Bhawanpreet Lakha
Date: Thu Mar 15 13:01:46 2018 -0400
drm/amd/display: Add Dynamic debug prints
Created Macros for DC_LOG_XXX to pr_debug()
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
The functions insert into the output resource creation, and property
change functions. CRTC destroy is also hooked-up for proper cleanup of
the CRTC
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This change adds a few functions in preparation of enabling CRTC color
managment via the randr interface.
The driver-private CRTC object now contains
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
In cases where CRTC properties are updated without going through
RRChangeOutputProperty, we don't update the properties in user land.
Consider setting
On 2018-04-09 10:10 AM, Michel Dänzer wrote:
Hi Leo,
apologies for the late follow-up; I was on vacation and then backlogged.
No worries, thanks for the review :)
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
These patches will
On 2018-04-10 04:44 PM, Harry Wentland wrote:
Ping
On 2018-04-09 02:06 PM, Harry Wentland wrote:
Signed-off-by: Harry Wentland
Reviewed-by: Leo (Sunpeng) Li
---
drivers/gpu/drm/amd/display/include/logger_types.h | 2 +-
1 file changed, 1
On 2018-04-11 04:48 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The functions insert into the output r
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
In cases where CRTC properties are updated witho
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This change adds a few functions in preparation
On 2018-04-12 06:30 AM, Michel Dänzer wrote:
On 2018-04-11 11:26 PM, Leo Li wrote:
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
Hmm. So either legacy or non-legacy clients won't work at all, or
they'll step on each other's toes, clobbering the HW gamma LUT from
each other.
I'm afraid
.
Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
Thanks Harry,
Reviewed-by: Leo Li <sunpeng...@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_d
On 2018-06-15 02:57 AM, Michel Dänzer wrote:
On 2018-06-14 09:49 PM, Leo Li wrote:
On 2018-06-14 12:57 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new
patchset. Pe
On 2020-05-06 3:47 p.m., Nicholas Kazlauskas wrote:
[Why]
We're the drm vblank event a frame too early in the case where the
^sending
Thanks for catching this!
Reviewed-by: Leo Li
pageflip happens close to VUPDATE and ends up blocking the signal.
The implementation in DM
On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
[AMD Official Use Only]
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl
On 2021-08-16 9:59 a.m., Leo Li wrote:
On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
[AMD Official Use Only]
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/a
in
pipe_ctx
Series LGTM,
Reviewed-by: Leo Li
Thanks!
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 55 ++--
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 158 +--
.../dc/dml/dcn20/display_rq_dlg_calc_20.h | 4
List
Cc: Arnd Bergmann
Cc: Leo Li
Cc: Alex Deucher
Cc: Christian König
Cc: Xinhui Pan
Cc: Nathan Chancellor
Cc: Guenter Roeck
Cc:l...@lists.linux.dev
---
Reviewed-by: Leo Li
@@ -106,6 +106,7 @@ GPIO_DCN30 = hw_translate_dcn30.o hw_factory_dcn30.o
AMD_DAL_GPIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn30/,$(GPIO_DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN30)
+
Looks like we can drop this newline. Otherwise,
Reviewed-by: Leo Li
endif
On 2022-02-15 16:44, Alex Deucher wrote:
From: Prike Liang
- set DC version
- add construct/destroy dc clock management function
- register dcn interrupt handler
Signed-off-by: Prike Liang
Acked-by: Leo Li
Reviewed-by: Leo Li
Thanks.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm
On 2022-02-15 16:44, Alex Deucher wrote:
From: Prike Liang
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Reviewed-by: Leo Li
Thanks!
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
there's a quick fix, we should
revert for now. It sounds like this can break existing support for
PSR/PSR SU.
Acked-by: Leo Li
- Leo
Bhawan
*From:* LIPSKI, IVAN
*Sent:* October 2, 2023 1:47 PM
*To:* amd-gfx@lists.
is being enabled?
It causes a regression in amd_psr. Unless there's a quick fix, we should
revert for now. It sounds like this can break existing support for
PSR/PSR SU.
Acked-by: Leo Li
- Leo
Bhawan
*From:* LIPSKI, IVAN
On 2023-08-18 04:25, Melissa Wen wrote:
On 07/26, Aurabindo Pillai wrote:
This reverts commit 6c8ff1683d30024c8cff137d30b740a405cc084e.
This patch causes IGT test case 'kms_atomic@plane-immutable-zpos' to
fail on AMDGPU hardware.
Cc: Joshua Ashton
Signed-off-by: Nicholas Choi
---
: PSR-SU rate control support in DC
Leo Li (1):
drm/amd/display: Implement MPO PSR SU
A couple of suggestions from Daniel on IRC:
1. Might be good to extract the "calculate total crtc damage" code
from i915 in intel_psr2_sel_fetch_update, stuff that into damage
helpers and reus
(
ln_align->raw = dpcd_buf[2];
if (is_repeater(link, offset)) {
+
With this extra newline dropped,
Reviewed-by: Leo Li
Thanks!
DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
" 0x%X Lane01Status = %x\n 0x%X L
On 2022-07-12 13:00, Alex Deucher wrote:
On Tue, Jul 12, 2022 at 12:28 PM wrote:
From: Leo Li
When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain w
DPCD caps
0x70su_y_granularity 4 force_psrsu_cap **X**
Thanks,
Leo
On 2022-09-23 16:26, August Wikerfors wrote:
Hi Leo,
On 2022-09-23 20:41, Leo Li wrote:
Hi August,
Can you provide a dmesg log with drm.debug=0x16 enabled in kernel
cmdline?
Log is available here:
https://nam11.safelinks.protection.outloo
On 2022-09-28 10:53, Hamza Mahfooz wrote:
On 2022-09-28 10:49, sunpeng...@amd.com wrote:
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used
On 2022-09-28 09:52, Harry Wentland wrote:
On 2022-09-27 19:13, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we
Hi August,
Can you provide a dmesg log with drm.debug=0x16 enabled in kernel cmdline?
I wasn't aware that there are currently psr su edp panel + rembrandt apu
systems out in the wild. In any case, psrsu + rmb should be working, and
there might something specific to your configuration that's
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr feature continues to be enabled for non capable links.
Do you have more info on what
On 2022-10-06 03:46, S, Shirish wrote:
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr
On 2022-10-07 00:28, Shirish S wrote:
[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.
[How]
explicitly disable the feature on links that are not capable of the same.
Signed-off-by: Shirish S
Reviewed-by: Leo Li
Thanks
Hi August,
I've sent a fix here: https://patchwork.freedesktop.org/patch/504993/
It's not the most ideal fix, but it should address the regression. Let
me know it works for you.
Thanks!
Leo
On 2022-09-27 10:22, August Wikerfors wrote:
Hi Leo,
On 2022-09-27 00:29, Leo Li wrote:
Hi
On 1/5/23 15:07, Hamza Mahfooz wrote:
On 1/5/23 13:29, Harry Wentland wrote:
On 1/5/23 12:38, Hamza Mahfooz wrote:
Currently, there are issues with enabling PSR-SU + DSC. This stems from
the fact that DSC imposes a slice height on transmitted video data and
we are not conforming to that
On 11/15/22 15:24, Hamza Mahfooz wrote:
Currently, userspace doesn't have a way to communicate selective updates
to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer
than DCN301, convert DRM damage clips to dc dirty rectangles and fill
them into dirty_rects in
in fill_dc_dirty_rects().
Signed-off-by: Hamza Mahfooz
Thanks for the patch, it LGTM.
Reviewed-by: Leo Li
It would be good to add an IGT case to cover combinations of MPO &
damage clip commits. Perhaps something that covers the usecase of moving
a MPO video, while desktop UI updates. We'd expect th
: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
...@amd.com
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 -
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 54 +++
2 files changed, 56 insertions
() that are only useful for debugging PSR
(and confusing otherwise). So, we can instead limit the filling of dirty
rectangles to only when PSR is enabled.
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks
---
v2: give a more concrete reason.
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7
this commit: b261509952bc19d1012cf732f853659be6ebc61e.
b261509952bc19d1012cf732f853659be6ebc61e is the first bad commit
commit b261509952bc19d1012cf732f853659be6ebc61e
Author: Leo Li
Date: Tue Aug 30 16:38:16 2022 -0400
drm/amd/display: Fix double cursor on non-video RGB MPO
[Why]
firmware.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn314/dcn31/ mixup
---
drivers/gpu/drm/amd/display/amdgpu
: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn31/dcn314/ mixup
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c | 5 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h | 2 ++
drivers/gpu/drm/amd/display/dmub/
in
fill_dc_dirty_rect().
Cc: sta...@vger.kernel.org # 6.1+
Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks!
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 -
1 file changed, 4 insert
On 6/22/23 14:25, Mario Limonciello wrote:
This reverts commit 33eec907ce0eb50a56dca621aa7310f7fa904b93.
This is no longer necessary when using newer DMUB F/W.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
-by: Mario Limonciello
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 7c9a2b34bd05..2a66a305679a 100644
On 6/22/23 14:25, Mario Limonciello wrote:
A number of parade TCONs are causing system hangs when utilized with
older DMUB firmware and PSR-SU. Some changes have been introduced into
DMUB firmware to add resilience against these failures.
Don't allow running PSR-SU unless on the newer
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