Re: [Amforth] Watchdog Timer on AVR8s
I should add this is a follow-up to a thread started in 2019. Here's the archive of that thread: https://sourceforge.net/p/amforth/mailman/message/36683433/ -- Regards, Martin Nicholas. E-mail: m...@mgn.org.uk. ___ Amforth-devel mailing list for http://amforth.sf.net/ Amforth-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/amforth-devel
Re: [Amforth] Watchdog Timer on AVR8s
Hi, I've had this one brewing for some time. Looking at schemes for: AT90CAN128 & ATA6612C. Common variables between chips: WDTCSR (WDTCR), WDTOE (WDCE), WDCE, WDE. WDTCSR & WDTOE are included "For compatibility" in the CAN chip. I include this in cold.asm. It should work with the two WDTs in the chip series above as well as chips with no WDT at all: .if defined(WDTCSR) ; There's a WDT, so we reset it as per the docs. in_ temp0, WDTCSR ori temp0, (1
Re: [Amforth] Watchdog Timer on AVR8s
Hi, Thanks for your analysis. > This suggests that both the MCUSR and the WDTSR should be cleared on > reset. > > I've added a line: > out_ WDTCSR, zerol > to COLD which covers it. adding it to COLD in a central location is troublesome. Not all AVR8 have a watchdog at all and those who have one, have at least two different ways to handle it. Rather difficult to implement centrally. > > The minimum requirement is to clear both MCUSR.WDRF and WDTCSR.WDE. AFAIK, the minimum reset intervall is 15ms, what makes it possible to add the reset code to the application turnkey word. For debugging purposes, the reset recipe may be helpful http://amforth.sourceforge.net/TG/recipes/Reset.html Matthias ___ Amforth-devel mailing list for http://amforth.sf.net/ Amforth-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/amforth-devel
Re: [Amforth] Watchdog Timer on AVR8s
This snippet is a bit more like it (I think): lds temp0, WDTCSR ori temp0, (1
