On 01/09/2015 01:12 AM, Slichter, Daniel H. wrote:
> You mean to use essentially as a thresholding phase detector? In
> other words, directly measuring the phase of the output signal
> instead of the phase of the SYNC_CLK?
Yes.
> We could potentially
> implement this, but I would do it in additi
> > If we are OK with losing the back-compatibility with previous designs, we
> can think about using high-speed connectors e.g. SAMTEC QRM8, which are
> designed for this sort of thing.
How about this solution: we use an inexpensive high-speed board-edge connector
(Samtec HSEC8-DV:
http://www
> Well, synchronizing them to one SYSCLK provides an elegant solution to this
> problem and that of meeting setup times on all chips, at the cost of having
> another skew-matched layout for the distribution buffer to flip-flop lines. As
> I believe you can add more layers to the backplane in the wo
On 01/08/2015 07:17 AM, Slichter, Daniel H. wrote:
>> The phase of that distant DDS will also be off by roughly the
>> propagation delay.
>
> See above; this is not an issue because we don't really care about
> the absolute phase difference between DDS chips at the plane of the
> DDS outputs, just
> > This is part of why I have been proposing LVCMOS signals instead of
> > trying for crazy bandwidths with differential signaling -
>
> I don't see how LVCMOS helps with signal integrity over pin headers given
> that the bandwidth depends on the requirement on the rise time of the
> signal (and
> If they are not aligned at the DDS chips, then setting the same phase on two
> different DDS channels is difficult and requires knowledge of how much the
> skew is. Essentially, the phase reference would be different for each DDS
> channel.
This doesn't actually matter -- all we need is that the
On Tue, Jan 6, 2015 at 5:41 PM, Slichter, Daniel H.
wrote:
>> What connector do you want to use to get these fast-edge signals from the
>> backplane to the dds cards and back?
>
> This is part of why I have been proposing LVCMOS signals instead of trying
> for crazy bandwidths with differential s
On 01/07/2015 02:02 AM, Slichter, Daniel H. wrote:
>> All SYNC_CLKs need to be matched (ideally to less than a SYSCLK
>> cycle) so that the FPGA can properly detect when they are aligned,
>> and a shared bus will not achieve that.
>
> This is not necessarily required, I had thought. What we nee
> What connector do you want to use to get these fast-edge signals from the
> backplane to the dds cards and back?
This is part of why I have been proposing LVCMOS signals instead of trying for
crazy bandwidths with differential signaling - the current design calls for the
use of 2mm pin headers
On Tue, Jan 6, 2015 at 12:14 PM, Slichter, Daniel H.
wrote:
> So now the system would have the following components on the FMC backplane
> and DDS cards:
>
> * SYNC_IN 1:12 clock distribution with lines to each DDS, driven by FPGA with
> variable ODELAY
> * SYNC_CLK LVCMOS-to-LVPECL latch on eac
> On 01/06/2015 03:26 PM, Sébastien Bourdeauducq wrote:
> > Or sample SYNC_CLK with a discrete flip-flop or latch near each DDS
> > chip and trigger them with a skew-matched on-board clocking network
> > pulsed by the FPGA through a scanned ODELAY. Then low-performance
> > multiplexers, shared buse
> That sounds reasonable. What about using LVDS and two male SMA
> connectors, e.g.:
> http://www.digikey.com/product-
> detail/en/CONSMA013.031/CONSMA013.031-ND/1577227
> soldered on the back of the LTC6957 PCB? They would serve both as a short
> electrical connection and mechanical mount. I suppo
On 01/06/2015 03:26 PM, Sébastien Bourdeauducq wrote:
> Or sample SYNC_CLK with a discrete flip-flop or latch near each DDS chip
> and trigger them with a skew-matched on-board clocking network pulsed by
> the FPGA through a scanned ODELAY. Then low-performance multiplexers,
> shared buses and skew
On 01/06/2015 01:55 PM, Sébastien Bourdeauducq wrote:
> Routing each SYNC_CLK to the FPGA with matched trace lengths all the way
> is also an option. Using one IDELAY and one IOB register per input (all
> clocked from the same network) should result in low skew.
Or sample SYNC_CLK with a discrete
Hi,
On 01/06/2015 04:43 AM, Slichter, Daniel H. wrote:
> Is there an on-die 100-ohm differential termination for LVDS signals
> at VCCO = 2.5V?
Yes.
> Either way, it's actually a physically shorter distance from the SMA
> connector to the FPGA (~5 cm) than from the FMC connector to the
> FPGA,
> >> I'm not very confident about this technique (and high speed LVDS
> >> signals on two separate SMA connectors in general). The differential
> >> impedance will not match the LVDS requirements on long sections of
> >> the transmission line.
> >
> > Another option is to use a single-ended 2.5V LV
On 01/03/2015 06:47 AM, Slichter, Daniel H. wrote:
>> I'm not very confident about this technique (and high speed LVDS
>> signals on two separate SMA connectors in general). The
>> differential impedance will not match the LVDS requirements on long
>> sections of the transmission line.
>
> Another
> On 01/01/2015 01:21 AM, Slichter, Daniel H. wrote:
> > For the RTIO clocking, I'm currently planning to put a 2.5V LVDS clock
> > on the USER_CLK_P/USER_CLK_N SMA connectors directly on the
> > KC705 board (goes to an MRCC pair in I/O Bank 15, pins L25 and K25).
>
> I'm not very confident about
Hi,
Happy new year to all!
On 01/01/2015 01:21 AM, Slichter, Daniel H. wrote:
> For the RTIO clocking, I'm currently planning to put a 2.5V LVDS
> clock on the USER_CLK_P/USER_CLK_N SMA connectors directly on the
> KC705 board (goes to an MRCC pair in I/O Bank 15, pins L25 and K25).
I'm not very
Hi Sebastien (cc'ing ARTIQ list for commentary/archival purposes),
For the RTIO clocking, I'm currently planning to put a 2.5V LVDS clock on the
USER_CLK_P/USER_CLK_N SMA connectors directly on the KC705 board (goes to an
MRCC pair in I/O Bank 15, pins L25 and K25). This will come from an LTC69
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