Good points; I understand the issue better now. I'm OK with removing this
feature.
Jonathan Mizrahi
Research Scientist
Joint Quantum Institute
University of Maryland
301-314-1903
On Wed, Nov 23, 2016 at 3:29 PM, Robert Jördens <r...@m-labs.hk> wrote:
> On Wed, Nov 23, 2016 at 9:16 PM,
>
> leads to overhead and is unergonomic/unaesthetic.
>
Can you clarify how you find this unaesthetic? From the perspective of an
ARTIQ user, having to check for zero pulse lengths everywhere seems to
create far more unaesthetic programs.
I also second Daniel's point -- we often scan pulse
Yes, there are CS lines, and I can use them, if I physically short the data
lines. As it appears I have to short them to avoid having to make a bunch
of changes, I would rather virtually short them in software. How do you
recommend I do that?
Jonathan Mizrahi
Research Scientist
Joint Quantum
suppose, just short the two data lines and use SPI "correctly." I
would prefer, though, a software solution, as I really don't want to modify
my hardware.
Jonathan Mizrahi
Research Scientist
Joint Quantum Institute
University of Maryland
301-314-1903
On Fri, Oct 28, 2016 at 11:10 AM, Slichter
subsignals to not be specific
pins, but rather be determined by a mux internal to the FPGA. How do I do
that?
Jonathan Mizrahi
Research Scientist
Joint Quantum Institute
University of Maryland
301-314-1903
On Fri, Oct 28, 2016 at 9:03 AM, Sébastien Bourdeauducq <s...@m-labs.hk>
wrote:
>
In the platform extension file, when I specify the SPI buses, there is a
clock subsignal "clk." If I want to have multiple SPI buses that share the
same clock, I'm going to need to reference the same clock subsignal in each
bus, which means that that specific pin will appear multiple times in the
mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Robert
> > Jördens
> > Sent: Monday, September 19, 2016 4:57 PM
> > To: Jonathan Mizrahi <jmizr...@umd.edu>
> > Cc: artiq@lists.m-labs.hk
> > Subject: Re: [ARTIQ] 3.3 V I/O on kc705
> >
> > On Mon, Sep
Hello,
I would like to operate peripherals on the kc705 FMC HPC connector at 3.3
V, both input and output. Can this be achieved by just setting the
IOStandard to LVCMOS33 in the fmc_adapter_io list in the gateware?
I ask because the kc705 manual states that all the I/O voltage rails are
set to
Hello,
How do I determine what FPGA pins on the KC705 FMC HPC connector are
capable of being used for the high resolution serdes TTL in/outs? I could
not find this information in the SelectIO resources guide from Xilinx, in
the section for ISERDESE2 and OSERDESE2. Can all general I/O be routed as
From: Robert Jördens [r...@m-labs.hk]
Sent: Wednesday, May 25, 2016 4:48 PM
To: Jonathan Mizrahi
Cc: artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] connecting to KC705
Hey Jonathan,
On Wed, May 25, 2016 at 10:34 PM, Jonathan Mizrahi <jmizr...@umd.edu> wrote:
> I get "
Hello,
I am having trouble running artiq on the KC705. I am going through the
installation instructions, and I believe I have successfully flashed the
bit files. I then flashed the mac address and IP, using the commands:
> artiq_mkfs flash_storage.img -s mac 1A:2B:3C:4D:5E:6F -s ip
is the fastest way to get to the point of controlling the
KC705 board?
Thanks for the help!
Jonathan
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Tuesday, March 15, 2016 10:49 PM
To: artiq@lists.m-labs.hk
Cc: Jonathan Mizrahi <jmizr...@umd.edu>
Subje
s. Any help in getting up and running with the KC705 would be very
appreciated.
Thanks,
Jonathan Mizrahi
Research Scientist
Joint Quantum Institute
University of Maryland
301-314-1903
___
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
13 matches
Mail list logo
