You can make a macro that will do this. At Amdahl we had such at one time.
Where I currently work, we have a macro called ALIGN. It was developed long
before the G3 chipset (where 256byte cache lines came about IIRC).
If you make use of you could control how your expansion works, by
passing
the difference is the option used
THREAD
NOTHREAD
Default THREAD
THREAD Specifies that the assembler not reset the location counter to zero
at the beginning of each CSECT.
NOTHREAD Specifies that the assembler reset the location counter to zero at
the beginning of each CSECT, except for the
Your listing confused me. At the latest HLASM version (UI42852) I get:
LocObject Code Addr1Addr2Stmt Source Statement
1 * from ASSEMBLER-LIST
24/11/2016
0032 2 PREXRL RSECT
> What effect does an unconditional branch have on branch
prediction/pipelining?
> Is LOCTR a help? I can imagine the frustration of a programmer trying
to
> Does HLASM have an instruction to cause cache line alignment? Such an
> instruction would need to be model-sensitive, perhaps governed by
The closet instruction is HLASM has for what Gil asked is CNOP - updated a
couple of years ago by apar PI17455 - but you do need to know what your
cache lines are.
see http://www.ibm.com/support/docview.wss?uid=isg1PI17455
and http://www.ibm.com/support/docview.wss?uid=swg21687009
Where the
