L1 cache should keep up with the processor. It is 128K or 512 lines of L1
cache, so if the data you are working on will fit in L1 and not roll it, then
that should not be your problem.
L1.5 is about 8 times slower than L1, if memory serves me correctly.
The other thing to consider is the
All of these are pipeline issues. Bob Rodgers did a good presentation at Share
in Boston of 2010, session 7534. There are several other papers out on the web
that go into the internals of the machines in great detail.
First of all there are 2 types of instructions, those that are executed 'on
Multiple ATTACH's mean one copy of the programs in memory, at least of those
routines written reentrant. Multiple address spaces means multiple copies in
memory, unless you put the modules in LPA, and all the other overheads
associated with an address space.
I don't know the memory
Working off the standards laid out in the Assembler Services Guide as copied
here:
Unless otherwise defined by the individual interface, the calling program should
expect, upon return, that
v The low halves (Bits 32-63) of GPRs 2 through 13 are unchanged
v The high halves (Bits 0-31) of GPRs 2
The answer comes from the POP manual.
The displacement for LA is treated as a 12-bit
unsigned binary integer. The displacement for LAY is
treated as a 20-bit signed binary integer.
It is perfectly legal and appropriate for the LAY to go negative.
Christopher Y. Blaicher
Senior Software
To someone writing performance code, and why else would you be writing
assembler, MVCL/CLCL/etc are terrible instructions performance-wise unless you
are moving over 32K of data.
In answer to the original question, there is no space in the instruction to add
the bits. Changing the system to
