Already exists from IBM: Prime PSA.
Keith Moe
Amdahl/BMC retired
On Wednesday, March 29, 2023, 04:24:25 PM PDT, Charles Mills
wrote:
Did anyone suggest this before?
On ***a test system only*** writing a special privileged program to fill all of
the addresses from 0 to x'7F
Nucleus.
Keith
Sent from an iPhone
> On Nov 18, 2022, at 09:50, Peter Relson wrote:
>
> You ignore the message at your own risk.
>
> Unless your module is page-aligned and this is a page-aligned CSECT within
> that module, you have no idea if the CSECT will land on a quadword (or
>
No need for logical loading of an 8 byte number. There is no sign propagation,
so a simple LG will do. The, the arithmetic would use ALG, SLG, etc.
Keith Moe
BMC Software (retired in 33 days)
On Thursday, April 28, 2022, 02:20:56 PM PDT, Schmitt, Michael
wrote:
How did you do
This already exists in the OS: PGSER RELEASE.
Keith Moe
BMC Software
Soon retired
On Thursday, April 14, 2022, 12:41:27 PM PDT, Seymour J Metz
wrote:
How about something a bit more complicated that let's the OS know that it can
do a page steal without having to page it out to DASD
Should this:
.SKIP_NFG MEND
.BAD_C MNOTE 8,'C must be between 0 and 63.'
MEND
Be:
.SKIP_NFG MEXIT <==
.BAD_C MNOTE 8,'C must be between 0 and 63.'
MEND
Keith Moe
BMC Software (until May 31st)
On Friday, March 4, 2022, 03:10:53 PM PST, Dan Greiner
wrote:
More than
Actually the inline TR/EX will do the TR the first time for ONE byte, not 256,
followed by the EX of the specified length.
Keith Moe
BMC Software
On Thursday, November 11, 2021, 01:44:07 PM PST, Seymour J Metz
wrote:
There are bigger problems than cache in that example; the EX/TR
generated by the IEABRCX macro (BRC n, label
instead of JE/H/L/etc.), so I change all of the open code and have IEABRCX
handle the macros I have no control of.
Keith Moe
BMC Software On Sunday, November 7, 2021, 05:54:10 PM PST, Tony Thigpen
wrote:
I don't think putting a LTORG in my macro would
How about this:
00256A E801 8011 C133 00011 0263B 7340 MVCIN NDX$CEI+1,=C'ab'+L'=C'ab'-1
00263A 8182 7437 =C'ab'
10 20098+NDX$CEI DS H
Keith Moe
BMC Software, Inc.
On Friday, October 23, 2020, 03:33:37 PM PDT, Charles Mills
wrote:
Can you code an address expression
Suppose the return address is loaded into R14 instead of a link type
instruction and R14 points to the first byte of a page
In addition, when a program is attached, R14 usually points to CVTEXIT (SVC 3)
and the halfword before it is some vector value.
Keith Moe
BMC Software, Inc
are in our vocalizations of
"non-words".)
Keith Moe
BMC Software
On Thursday, January 30, 2020, 12:17:47 PM PST, Seymour J Metz
wrote:
There's a reason that I never had a job as a typist. You're right, of course,
that I meant S0C1.
I used to use SPIE to distinguish betwe
IEC020I in z/OS MVS System Messages, Vol 7 (IEB-IEE) for
information about the task that was ended.
S001 and S0C1 have nothing to do with each other.
Keith Moe
BMC Software
On Thursday, January 30, 2020, 11:38:53 AM PST, Seymour J Metz
wrote:
Not quite; ABEND S001 indicates
.
Keith Moe
BMC Software, Inc.
On Wednesday, January 29, 2020, 1:47:35 PM PST, John McKown
wrote:
Cheat -- use the ABEND macro. Yes, you can use it to generate system anend
codes.
PIC 5 is basically that a physical address doesn't exist, so I doubt you
can generate it DAT on.
On Wed, Jan
quot; user of a BALR instruction to set the base
register with an offset of 2 (which he didn't like - and neither do I). I
started with DOS and TOS in 1966 and you had to do this because no register was
set as the main program entry point when you received control.
Keith Moe
BMC Software
On Mond
was reduced by not freeing the
buffers that might be reused.
When 31-bit buffers were implemented, they did not perpetuate this design.
Keith Moe
BMC Software
On Thursday, July 11, 2019, 7:45:15 AM PDT, Seymour J Metz
wrote:
FREEPOOL has always been a requirement for a straight QSAM DCB
Years ago I suggested the need for an ACOPY statement that would only be
processed if conditional assembly did not bypass it. But I never created a
Share requirement or RFE.
Keith
Sent from an iPhone
> On Mar 8, 2019, at 12:37, Paul Gilmartin
>
pointing to CVTEXIT. The CVT is in the read/write nucleus and is not even
cache line aligned!
Keith Moe
BMC Software, Inc.
On Wed, 8/1/18, Charles Mills wrote:
Subject: Re: EQU * considered harmful
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Date: Wednesday
CONSTANTS (not updatable
areas), I generally avoid mixing instructions and data. Even in non-reentrant
code (unfortunately there's a lot here that I have to maintain and it's not
worth it to make it reentrant), I try to isolate code blocks and data blocks.
Keith Moe
BMC Sof
on, this
could also be considered a warning situation. In the situation where the
instruction is generated via non-standard means (i.e., DC X'' because the
Opcode does not have a mnemonic), the ACONTROL function could be used to avoid
the warning.
Keith M
you spend a lot of time debugging problems occurring in customer
production environments, life can be difficult.
Optimization is great until it isn't!
Keith Moe
Lead Developer
BMC Software, Inc.
On Mon, 1/29/18, Martin Ward <mar...@gkc.org.uk> wrot
, especially in uniprocessor LPARs. The products I work
on have DIE and RISGNL (SIGP) routines that run disabled. We've had our share
of "Oh, *&^%*!" over the years, fortunately few and far between and none
recently.
Keith Moe
BMC Software
On Tue
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