If you provide the option of specifying labels or literals, it is up to the
end user to provide addressability to the literals.
I would not be against a keyword such as PERFORMANCE=CRAP to force the data
items inline so that no end-user data area is needed.
On Mon, 8 Nov 2021 09:09:42 +0100
The documentation update for APAR PH34824, for the alignment of
literals referenced by relative address, has now been completed.
https://www.ibm.com/docs/en/hla-and-tf/1.6?topic=instruction-literal-pool
It seems it was overlooked after being transferred from our old
request tool to the new - a
I'm reluctant to admit this, but I'm still unclear about SIIS issues. Could
someone please explain what happens to the D- and I-cache in these situations?
Example 1:
TxtTRNull TR0(*-*,R14),NoNulls
EX R5,*-6
Example 2:
PgmConst LOCTR ,
TxtTRNull TR
For the first 2 examples, those are not SIIS violations because no
modification of storage takes place. The modification of the instruction
happens in the core itself (I once heard it called the "instruction
register" where this happens... I can't verify the validity of that
statement).
In
How do you ensure that your storage areas are far enough away from the code to
not be in the instruction cache line, when your data isn't in GETMAIN storage?
You can mitigate by putting constants in between, but how do you know if that's
enough?
For current processors, 256 bytes.
Some IBMers talking with us on these topics suggested a macro called
NEXTCLB,
which inserts some space depending on some address arithmetic.
IMO, if you use this, you could adjust it later if a future processor
requires more.
(256 is a constant used inside
On Wed, 10 Nov 2021 at 11:45, Wendell Lovewell
<09624390d784-dmarc-requ...@listserv.uga.edu> wrote:
>
> I'm reluctant to admit this, but I'm still unclear about SIIS issues. Could
> someone please explain what happens to the D- and I-cache in these situations?
I can tell you my
