Re: Microprocessor Optimization Primer

2016-04-03 Thread Steve Smith
I was referring to the last bullet on page 44, "Regular register clearing instructions are fast-pathed in the pipeline; and their results do not use any physical registers (since zEC12)". The sub-bullets mention XR (& XGR), but not SR, SLR, etc. So I may have assumed too much. On the other

Re: Microprocessor Optimization Primer

2016-04-03 Thread Gord Tomlin
On 2016-04-02 14:13, John P. Hartmann wrote: Last I heard SLR was seriously discouraged. because it stalls the pipeline where the others don't. I hadn't heard that one, but would be quite interested to hear whether it is true. -- Regards, Gord Tomlin Action Software International (a