I was referring to the last bullet on page 44, "Regular register
clearing instructions are fast-pathed in the pipeline; and their results
do not use any physical registers (since zEC12)". The sub-bullets
mention XR (& XGR), but not SR, SLR, etc. So I may have assumed too much.
On the other hand, I can't imagine any reason why SLR would "stall the
pipeline" all by itself; or act any differently than SR in particular.
And those are "regular register-clearing instructions" in my mind. But,
I'm not by any means an expert on the processor architecture.
There are a few oddities in the architecture, such as BR 0 (and now BCR
14,0) that cause the CPU to do odd things, but those are particular
instructions that have no other use, and are documented.
sas
On 4/2/2016 14:13, John P. Hartmann wrote:
Are you speaking from knowledge?
Last I heard SLR was seriously discouraged. because it stalls the
pipeline where the others don't.
On 04/02/2016 06:43 PM, Steve Smith wrote:
All the same (and they're all optimized),
