[PATCH 11/11] firmware: Fix copy-paste comment mistake

Signed-off-by: Andrey Smirnov --- firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index 62124933d..7f4dc4932 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -57,6 +57,6 @@ endif targets := $(patsubst

[PATCH 07/11] ARM: i.MX: fimware: Add pre-built BL31 ATF blob

Running Linux on i.MX8M requires us to use and proerly set up a ARM Trusted Firmware blob. For the sake of convenience, add a pre-built blob to our firmware tree, so it can be used by individual boards. This blob was built using Buildroot: - commit: 6b02b8210acb18773f2c4b26cfc11d1f9bc4fb88 -

[PATCH 06/11] ARM: i.MX: xload-esdhc: Allow patching first word of the image

Depending on how SD card/eMMC was programmed first byte of the image ther may or may not have appropriate branch instruction. Extend esdhc_start_image() to allow passing a custom callback that would patch the first instruction in memory to correctly redirect the CPU to the resto of the code.

[PATCH 10/11] ARM: nxp-imx8mq-evk: Add bootflow comments

Add some notes on how the boot-flow goes while I still remember it. Signed-off-by: Andrey Smirnov --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 42 +-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c

[PATCH 09/11] ARM: i.MX8MQ: Query and display ATF fimware hash if availible

Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/imx8mq.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c index dbcf4fa59..152f07bc1 100644 --- a/arch/arm/mach-imx/imx8mq.c +++ b/arch/arm/mach-imx/imx8mq.c @@ -20,11

[PATCH 08/11] ARM: nxp-imx8mq-evk: Add code to load ATF BL31 blob

Signed-off-by: Andrey Smirnov --- arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 3 +++ arch/arm/mach-imx/Kconfig | 2 ++ firmware/Kconfig | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c

[PATCH 04/11] ARM: i.MX8MQ: Add a macro to load BL31 ATF blob

Add a macro containing all of the code needed to load and transfer control to BL31 ATF blob on i.MX8M. Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/include/mach/atf.h | 63 1 file changed, 63 insertions(+) create mode 100644

[PATCH 05/11] ARM: i.MX: xload-esdhc: Move image base to MX8MQ_ATF_BL33_BASE_ADDR

BL31 ATF implementation provided by NXP will jump to MX8MQ_ATF_BL33_BASE_ADDR after completing its initialization. Move image base used by imx8_esdhc_start_image() in order to support that. Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/xload-esdhc.c | 3 ++- 1 file changed, 2

[PATCH 03/11] ARM: i.MX8MQ: Configure cntfrq only in EL3

We only can (and should only need to) configure cntfrq when running in EL3 and executing this code in any other exception level will result in exception. Signed-off-by: Andrey Smirnov --- arch/arm/mach-imx/imx8mq.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git

[PATCH 02/11] ARM: Add code to support SMCCC on AArch64

Port SMCCC code from Linux kernel. To accomodate that: - Introduce CONFIG_ARM_SMCCC, to allow enabling the code independent of CONFIG_ARM_SECURE_MONITOR - Bring in - Add necessary constants to arch/arm/asm-offsets.c Signed-off-by: Andrey Smirnov --- arch/arm/Kconfig

[PATCH 00/11] ARM: i.MX8MQ and EVK support, part II

Everyone: This is part II of i.MX8MQ EVK board support patches. This time this is bits and pieces that were necessary in order to allow booting vendor Linux kernel availible here (tag: rel_imx_4.9.51_8mq_ga): https://source.codeaurora.org/external/imx/linux-imx Sources for ATF were taken

[PATCH 01/11] ARM: nxp-imx8mq-evk: Update DDR initialization code

Previous version of DDR initialization code was generated by a beta version of MX8_DDR_tool. This updates the code to the output of MX8_DDR_tool v1.0, which seem to fix the vendor Linux kernel hang* that was happening with the previous version. * The kernel would hang as soon as it tried to

[PATCH 2/3] ARM: dts: rdu1: Specify "boot-source" NVMEM cell

Signed-off-by: Andrey Smirnov --- arch/arm/dts/imx51-zii-rdu1.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index b0e1d0276..731565c0d 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++

[PATCH 3/3] ARM: dts: rdu1: Add node for backlight device

Signed-off-by: Andrey Smirnov --- arch/arm/dts/imx51-zii-rdu1.dts | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 731565c0d..f0a279bf0 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++

[PATCH 1/3] ARM: dts: rdu1: Add nodes for RAVE SP EEPROM

Signed-off-by: Andrey Smirnov --- arch/arm/dts/imx51-zii-rdu1.dts | 28 1 file changed, 28 insertions(+) diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 7984e5b32..b0e1d0276 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++

[PATCH] fixup! ARM: i.MX: Add support for ZII RDU1 board

--- Sascha: I tested "ARM: i.MX: Add support for ZII RDU1 board" patch as it is in "next" and it works as expected. Here's a couple of cosmetic fixes I'd suggest (feel free to ignore): - Drop all ZII_RDU1_DATAFLASH_* constants since now they are superfluous. Previous version of the

Re: [PATCH v4 10/10] ARM: i.MX: Add support for ZII RDU1 board

On Thu, Jun 28, 2018 at 11:57 PM Sascha Hauer wrote: > > Hi Andrey, > > On Wed, Jun 27, 2018 at 09:54:36PM -0700, Andrey Smirnov wrote: > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define ZII_RDU1_DATAFLASH "/dev/dataflash0" > > +#define

Re: [PATCH 2/2] ARM: i.MX bbu: support partitions starting at i.MX header

On Thu, Jun 28, 2018 at 11:50 PM Sascha Hauer wrote: > > The i.MX header is at an offset in the boot device, usually 0x400 bytes. > This patch adds a flag to support the case that the partition the image > is written to starts at that offset rather than 0x0. > > Signed-off-by: Sascha Hauer > ---

Re: [PATCH 1/2] ARM: i.MX bbu: reimplement IMX_INTERNAL_FLAG_KEEP_DOSPART flag

On Thu, Jun 28, 2018 at 11:49 PM Sascha Hauer wrote: > > This patch reimplements the IMX_INTERNAL_FLAG_KEEP_DOSPART flag > and makes it more generic. Until now we only kept a dos partition > table over the update. Beginning with i.MX8 we may also want to > preserve a GPT, so we have to extend the

Re: Troubles running qemu64 target

On Fri, Jun 29, 2018 at 2:01 AM Raphaël Poggi wrote: > > Hi Guillaume & Andrew, > > > Le ven. 29 juin 2018 à 01:46, Andrey Smirnov > a écrit : > > > > Guillaume: > > > > I haven't used QEMU ARM64 version of the code, but I have spent some > > time on i.MX8M which is ARM64 as well. See my

Re: [PATCH v2 03/12] Add initial RISC-V architecture support

On Fri, 29 Jun 2018 13:32:55 +0200 Sascha Hauer wrote: > On Fri, Jun 29, 2018 at 01:27:10PM +0300, Antony Pavlov wrote: > > On Fri, 29 Jun 2018 09:29:08 +0200 > > > > > > Do you need these __bare_init* stuff? If not I would prefer to remove > > > it. > > > > > > Hmmm. You are right! I have

Re: [PATCH] ARM: imx6qp: fix NoC QoS passthrough for new cpu type functions.

On Thu, Jun 28, 2018 at 06:29:05PM +0200, Philipp Zabel wrote: > On i.MX6QP/DP cpu_mx6_is_mx6q/d do not return true anymore. > Use the new cpu_mx6_is_mx6qp/dp to reenable NoC regulator bypass. > > Fixes: d4c05d29d484 ("ARM: i.MX6: Add cpu type for 'plus' variants") > Signed-off-by: Philipp Zabel

[PATCH v1 2/2] net: designware: make sure DMA is disabled on kernel start.

Halt is not automatically executed if we start the kernel. So, we may have potentially memory corruptions. Signed-off-by: Oleksij Rempel --- drivers/net/designware.c | 8 drivers/net/designware.h | 1 + drivers/net/designware_generic.c | 1 +

[PATCH v1 1/2] arm: arria10: enable errata 794072 and 845369

This SoC is affected by this two any many other erratas. So enable at least supported cases. Signed-off-by: Oleksij Rempel --- arch/arm/mach-socfpga/arria10-init.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/arria10-init.c

[PATCH v1 1/2] arm: arria10: enable errata 794072 and 845369

This SoC is affected by this two any many other erratas. So enable at least supported cases. Signed-off-by: Oleksij Rempel --- arch/arm/mach-socfpga/arria10-init.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/arria10-init.c

[PATCH v1 2/2] net: designware: make sure DMA is disabled on kernel start.

Halt is not automatically executed if we start the kernel. So, we may have potentially memory corruptions. Signed-off-by: Oleksij Rempel --- drivers/net/designware.c | 8 drivers/net/designware.h | 1 + drivers/net/designware_generic.c | 1 +

Re: [PATCH v2 03/12] Add initial RISC-V architecture support

On Fri, Jun 29, 2018 at 01:27:10PM +0300, Antony Pavlov wrote: > On Fri, 29 Jun 2018 09:29:08 +0200 > > > > Do you need these __bare_init* stuff? If not I would prefer to remove > > it. > > > Hmmm. You are right! I have not realized PBL for RISC-V yet so it's better > to drop all these

[PATCH] MIPS: don't include generated header files into MIPS asm files

This patch came out of discussions in the 'MIPS parallel build breakage' e-mail thread: http://lists.infradead.org/pipermail/barebox/2018-March/032251.html Signed-off-by: Antony Pavlov --- arch/mips/include/asm/pbl_macros.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff

Re: [PATCH v2 03/12] Add initial RISC-V architecture support

On Fri, 29 Jun 2018 09:29:08 +0200 Sascha Hauer wrote: > On Thu, Jun 28, 2018 at 10:39:44AM +0300, Antony Pavlov wrote: > > Signed-off-by: Antony Pavlov > > --- > > +++ b/arch/riscv/lib/barebox.lds.S > > @@ -0,0 +1,89 @@ > > +/* > > + * Copyright (C) 2016 Antony Pavlov > > + * > > + * This

Re: Troubles running qemu64 target

Hi Guillaume & Andrew, Le ven. 29 juin 2018 à 01:46, Andrey Smirnov a écrit : > > Guillaume: > > I haven't used QEMU ARM64 version of the code, but I have spent some > time on i.MX8M which is ARM64 as well. See my comments below. > > On Thu, Jun 28, 2018 at 6:46 AM ranquet guillaume > wrote: >

Re: [PATCH] ARM: i.MX53: Set pll3 directly to 216MHz.

On Thu, Jun 28, 2018 at 03:56:55PM +0200, Mogens Lauridsen wrote: > On Thu, Jun 28, 2018 at 10:30 AM, Sascha Hauer wrote: > > On Wed, Jun 27, 2018 at 04:07:11PM +0200, Mogens Lauridsen wrote: > >> PLL3 was first set to 400MHz and then some peripheral was switched > >> to PLL3. Finally PLL3 was

Re: [PATCH v2 00/12] Add initial RISC-V architecture support

Hi Antony, On Thu, Jun 28, 2018 at 10:39:41AM +0300, Antony Pavlov wrote: > This patchseries adds initial RISC-V architecture support for barebox. > > See Documentation/boards/riscv.rst for instructions. Applied patches 1 and 2 for now. The rest looks mostly fine except for the two suggestions

Re: [PATCH v2 03/12] Add initial RISC-V architecture support

On Thu, Jun 28, 2018 at 10:39:44AM +0300, Antony Pavlov wrote: > Signed-off-by: Antony Pavlov > --- > +++ b/arch/riscv/lib/barebox.lds.S > @@ -0,0 +1,89 @@ > +/* > + * Copyright (C) 2016 Antony Pavlov > + * > + * This file is part of barebox. > + * See file CREDITS for list of people who

Re: [PATCH v4 10/10] ARM: i.MX: Add support for ZII RDU1 board

Hi Andrey, On Wed, Jun 27, 2018 at 09:54:36PM -0700, Andrey Smirnov wrote: > +#include > +#include > +#include > +#include > +#include > + > +#define ZII_RDU1_DATAFLASH "/dev/dataflash0" > +#define ZII_RDU1_DATAFLASH_BAREBOX ZII_RDU1_DATAFLASH ".barebox" > + > +/** > + *

[PATCH 2/2] ARM: i.MX bbu: support partitions starting at i.MX header

The i.MX header is at an offset in the boot device, usually 0x400 bytes. This patch adds a flag to support the case that the partition the image is written to starts at that offset rather than 0x0. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx-bbu-internal.c | 7 +--

[PATCH 1/2] ARM: i.MX bbu: reimplement IMX_INTERNAL_FLAG_KEEP_DOSPART flag

This patch reimplements the IMX_INTERNAL_FLAG_KEEP_DOSPART flag and makes it more generic. Until now we only kept a dos partition table over the update. Beginning with i.MX8 we may also want to preserve a GPT, so we have to extend the preserved area. It might also be the case that not (only) a