Audio/Video PLL post dividers don't work on i.MX6q revision 1.0.
This helper can be reused in the upcoming workaround patch for
erratum ERR009219.
The check in the helper has been inverted to make it clearer which
platforms are affected. Old call site was adjusted to spell
out what is really happening nowadays (with clk-imx6.c covering
more variants than just i.MX6Quad and DualLite):
!rev1.0 || mx6dl
== !rev1.0 || !!mx6dl
== !(rev1.0 && !mx6dl)
== !(rev1.0 && (mx6s || mx6q || mx6qp || mx6d || mx6dp))
== !(rev1.0 && ((mx6q || mx6d) || (mx6s || mx6qp || mx6dp)))
== !((rev1.0 && (mx6q || mx6d)) || (rev1.0 && (mx6s || mx6qp || mx6dp)))
== (!(rev1.0 && (mx6q || mx6d)) && !(rev1.0 && (mx6s || mx6qp || mx6dp)))
== cpu_has_working_video_pll_post_div() && !(rev1.0 && (mx6s || mx6qp || mx6dp))
Signed-off-by: Ahmad Fatoum <a.fat...@pengutronix.de>
---
drivers/clk/imx/clk-imx6.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 35b995dae24e..88c4bcde1cb3 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -64,6 +64,12 @@ static inline int cpu_is_plus(void)
return cpu_is_mx6qp() || cpu_is_mx6dp();
}
+/* Audio/Video PLL post dividers don't work on i.MX6q revision 1.0 */
+static inline int cpu_has_working_video_pll_post_div(void) {
+ return !((cpu_is_mx6q() || cpu_is_mx6d()) &&
+ imx_silicon_revision() == IMX_CHIP_REV_1_0);
+}
+
static const char *step_sels[] = {
"osc",
"pll2_pfd2_396m",
@@ -341,8 +347,8 @@ static void imx6_add_video_clks(void __iomem *anab, void
__iomem *cb)
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
- cpu_is_mx6dl()) {
+ if (cpu_has_working_video_pll_post_div() &&
+ !((cpu_is_plus() || cpu_is_mx6s()) && imx_silicon_revision() ==
IMX_CHIP_REV_1_0)) {
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL],
clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
--
2.20.1
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