root= kernel cmdline parameter

Hi all, I'm trying to find out the best method to define the root= parameter when booting the linux kernel from barebox. My system boots from an sd card partitioned with a GPT. The sd card has two independent set of partitions with the following labels: 1) boot_1 + rootfs_1 2) boot_2 +

Help requested with Barebox on Globalscale Mirabox

Hello, I'm trying to get Barebox working on my Globalscale Mirabox, and I'm struggling. I have performed the following: 1. git clone git://git.pengutronix.de/barebox 2. cd into barebox and copy extracted binary.0 into arch/arm/boards/globalscale-mirabox/ 3. Edit

[PATCH 01/19] mci: dw_mmc: remove device_d pointer

The pointer to the struct device_d *dev is also saved to the struct mci_host. Get rid of it. Signed-off-by: Steffen Trumtrar --- drivers/mci/dw_mmc.c | 36 +--- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/mci/dw_mmc.c

[PATCH 10/19] ARM: socfpga: arria10: set default TEXTBASE

Signed-off-by: Steffen Trumtrar --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 58e4876f5c5e..4715e11434a6 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@

[PATCH 08/19] ARM: socfpga: add SMP_TWD_ADDR for Arria10

Signed-off-by: Steffen Trumtrar --- arch/arm/mach-socfpga/include/mach/arria10-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h index 931876f43a17..4464f0623187 100644 ---

[PATCH 04/19] bootm: allow booting SoCFPGA prebootloader image

From: Enrico Jorns A prebootloader image might also contain a fully working barebox and allows to be booted second stage. Thus we add a handler here to give it a try. Signed-off-by: Enrico Jorns --- arch/arm/lib32/bootm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[PATCH 00/19] ARM: SoCFPGA: Arria10: Early FPGA config

Hi! This series allows configuring the FPGA of an Arria10 SoCFPGA early in the bootprocess from barebox. Early means: before the SDRAM is used. The patches where developed for and tested on the Achilles board. While at it, some cleanup patches are included, too. Steffen Enrico Jorns (1):

[PATCH 02/19] mci: dw_mmc: convert to BIT() macro

Signed-off-by: Steffen Trumtrar --- drivers/mci/dw_mmc.c | 99 ++-- 1 file changed, 50 insertions(+), 49 deletions(-) diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index 0dd4c1f44154..473942cbe0f9 100644 --- a/drivers/mci/dw_mmc.c +++

[PATCH 06/19] ARM: socfpga: arria10: move debug_ll to common code

Instead of copy+pasting the debug_ll messages to every new board, move them to the respective functions. Signed-off-by: Steffen Trumtrar --- arch/arm/boards/reflex-achilles/lowlevel.c | 4 arch/arm/mach-socfpga/arria10-init.c | 2 ++ arch/arm/mach-socfpga/arria10-sdram.c | 2 ++

[PATCH 05/19] reset: socfpga: add missing driver name

The driver_d is missing the name property. When the reset driver is used in a non-of setup, this will result in an error during device_registration where the dev->name is matched to the driver->name. Signed-off-by: Steffen Trumtrar --- drivers/reset/reset-socfpga.c | 1 + 1 file changed, 1

[PATCH 17/19] ARM: socfpga: achilles: convert to PBL barebox

Previously the FPGA was configured externally on the Achilles. On newer versions this is changed and barebox has to configure the FPGA before the SDRAM can be used. If the FPGA is configured via JTAG or from an external memory, the *-bringup version can be used. Signed-off-by: Steffen Trumtrar

[PATCH 19/19] ARM: socfpga: achilles: move environment to raw partition

Signed-off-by: Steffen Trumtrar --- arch/arm/dts/socfpga_arria10_achilles.dts | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts index 0af7809adcce..60d99248dc46 100644 ---

[PATCH 07/19] ARM: socfpga: arria10: add ocram base address

Signed-off-by: Steffen Trumtrar --- arch/arm/mach-socfpga/include/mach/arria10-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h index 5569574e157d..931876f43a17 100644 ---

[PATCH 16/19] ARM: socfpga: Arria10: support programming FPGA in PBL

Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC

[PATCH 15/19] ARM: socfpga: arria10-reset-manager: don't reset bootsource

Arria10 init code resets all peripherals. Convert this to keep the bootmedium out of reset and keep the setup done by the boot ROM. Signed-off-by: Steffen Trumtrar --- arch/arm/mach-socfpga/arria10-bootsource.c | 16 +-- arch/arm/mach-socfpga/arria10-reset-manager.c | 33

[PATCH 03/19] mci: dw: move defines to headerfile

Signed-off-by: Steffen Trumtrar --- drivers/mci/dw_mmc.c | 115 +- drivers/mci/dw_mmc.h | 140 +++ 2 files changed, 141 insertions(+), 114 deletions(-) create mode 100644 drivers/mci/dw_mmc.h diff --git

[PATCH 13/19] ARM: dts: socfpga: Fix achilles dtc warnings

The newer dtc has stricter checks on devicetrees. Fix the warnings. Signed-off-by: Steffen Trumtrar --- arch/arm/dts/socfpga_arria10_achilles.dts | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts

[PATCH 14/19] scripts: socfpga_mkimage: add size feature for PBL barebox

Add the switch 's' to fixup the image size into the barebox header. This is used by the Arria10 PBL code to know the complete image size. Signed-off-by: Steffen Trumtrar --- scripts/socfpga_mkimage.c | 25 +++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git

[PATCH 12/19] ARM: socfpga: achilles: update handoff files

Signed-off-by: Steffen Trumtrar --- arch/arm/boards/reflex-achilles/pinmux-config-arria10.c | 2 +- arch/arm/boards/reflex-achilles/pll-config-arria10.c| 16 2 files changed, 9 insertions(+), 9 deletions(-) diff --git

[PATCH 11/19] ARM: socfpga: arria10: fix SDMMC phase shift

Signed-off-by: Steffen Trumtrar --- arch/arm/mach-socfpga/arria10-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c index 6a10c19d1417..53ec278739cc 100644 ---

[PATCH 09/19] ARM: socfpga: arria10-init: split pinsetup

Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed. Signed-off-by: Steffen Trumtrar --- arch/arm/boards/reflex-achilles/lowlevel.c | 1 + arch/arm/mach-socfpga/arria10-init.c | 49

[PATCH 18/19] ARM: arria10: update defconfig

Signed-off-by: Steffen Trumtrar --- arch/arm/configs/socfpga-arria10_defconfig | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig index e661895d6e6c..53e932d64b2a 100644 ---

Re: [PATCH 05/13] ARM: MXS: i.MX28: add autodetection of memory banks

Sascha, while looking for something different, I noticed the following patches in one of your personal branches: b2f6eeb Sascha Hauer ● ARM: i.MX28: Add memory size detection eb607ae Sascha Hauer ● ARM: i.MX23: Add memory size detection They look much cleaner than my patch, so if you