Re: How to configure and enable the barebox state?

[Sascha Hauer]

Hi Alain,

On Thu, Oct 13, 2016 at 01:38:36PM +, Trostel Alain wrote:
> Hi,
> 
> I would like to configure and enable the barebox state. My assumption is
> that I need to change the following device tree for my Phytec AM335x
> SOM:
> 
> arch/arm/dts/am335x-phytec-phycore-som.dts
> 
> But from the documentation
> (http://www.barebox.org/doc/latest/devicetree/bindings/barebox/barebox,state.html)
> it is not clear to me where exactly I need to add the variable node
> example.

You can put it anywhere in the device tree that is parsed by the device
parser. I would recommend putting it directly in the root node.

> Furthermore, I have check that the 'CONFIG_OFDEVICE' is
> enabled.
> So, where is the correct place to add the variable node configuration
> and what needs to be enabled in barebox?

for using the state framework you'll need:

CONFIG_STATE
CONFIG_STATE_DRV
CONFIG_CMD_STATE

If you want to use the bootchooser ontop of state you'll also need:

CONFIG_BOOTCHOOSER
CONFIG_CMD_BOOTCHOOSER

Sascha

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Industrial Linux Solutions | http://www.pengutronix.de/  |
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Re: Compressed DTB - builtin DTB

[Sascha Hauer]

Hi Daniel,

On Thu, Oct 13, 2016 at 12:32:31PM +0200, Daniel Krüger wrote:
> Hello,
> 
> I'm currently porting our board support to device tree. Currently, I don't
> use multi-PBL, but include the device tree via CONFIG_BUILTIN_DTB. This
> works, but the DTB seems to be included twice in the image: once as plain
> DTB and once as compressed DTB. I think this isn't intended this way.
> 
> Extract from System.map:
> 87e82b80 R __dtb_imx35_systec_hmi_start
> 87e82b80 R __dtb_start
> 87e8501c R __dtb_imx35_systec_hmi_end
> 87e85020 R __dtb_z_imx35_systec_hmi_start
> 87e85ad0 R __dtb_z_imx35_systec_hmi_end
> 87e85b00 B __bss_start
> 87e85b00 R __dtb_end

No, indeed that's not intended. Could you test the appended patch? It
should solve this.

> 
> Just using the compressed DTB would be really good. Because it makes the
> image much smaller. However, how should that be done? The extract code might
> be simple. But I don't have an idea how to let the linker select the right
> version.

If you are using uncompressed binary you should switch to PBL support to
get a compressed binary. Then, if you are using PBL the dtb is
compressed already as part of the whole binary.

Sascha

8<

>From c24a6bd6eabc3f73375080e6fc500aa955795a27 Mon Sep 17 00:00:00 2001
From: Sascha Hauer 
Date: Fri, 14 Oct 2016 11:42:00 +0200
Subject: [PATCH] gen-dtb-s: Put compressed dtb in different section

For builtin dtbs all compiled dtbs matching section .dtb.rodata.*
are collected in a single section. Since every dtb is compiled as
uncompressed and also as compressed binary each dtb ends up twice
in the section. Let's put the compressed variants in .dtbz.rodata.*
sections rather than .dtb.rodata.*.z so they end up in the binary
only once.

Signed-off-by: Sascha Hauer 
---
 scripts/gen-dtb-s | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/gen-dtb-s b/scripts/gen-dtb-s
index 40c6085..4215461 100755
--- a/scripts/gen-dtb-s
+++ b/scripts/gen-dtb-s
@@ -58,7 +58,7 @@ fi
 compressed=$(stat $dtb.lzo -c "%s")
 uncompressed=$(stat $dtb -c "%s")
 
-echo ".section .dtb.rodata.${name}.z,\"a\""
+echo ".section .dtbz.rodata.${name},\"a\""
 echo ".balign STRUCT_ALIGNMENT"
 echo ".global __dtb_z_${name}_start"
 echo "__dtb_z_${name}_start:"
-- 
2.9.3

-- 
Pengutronix e.K.   | |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

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[PATCH v2 3/3] ARM: socfpga: dtsi: add dw-wdt reset lines

[Steffen Trumtrar]

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/dts/socfpga.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index d16758fdab46..66d7f21dc6a3 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -49,3 +49,13 @@
 _sdram_ref_clk {
clock-frequency = <0>;
 };
+
+ {
+   resets = < L4WD0_RESET>;
+   reset-names = "dw-wdt";
+};
+
+ {
+   resets = < L4WD1_RESET>;
+   reset-names = "dw-wdt";
+};
-- 
2.9.3


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[PATCH v2 2/3] watchdog: add designware driver

[Steffen Trumtrar]

Port the linux v4.8-rc1 Synopsys DesignWare watchdog driver to barebox.

Signed-off-by: Steffen Trumtrar 
---
Changes since v1:
  - change usages of pr_warn in favor of dev_warn

 drivers/watchdog/Kconfig  |   6 ++
 drivers/watchdog/Makefile |   1 +
 drivers/watchdog/dw_wdt.c | 193 ++
 3 files changed, 200 insertions(+)
 create mode 100644 drivers/watchdog/dw_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 60a56bf4b030..63fb1a8c5701 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -16,6 +16,12 @@ config WATCHDOG_DAVINCI
help
  Add support for watchdog on the TI Davinci SoC.
 
+config WATCHDOG_DW
+   bool "Synopsys DesignWare watchdog"
+   select RESET_CONTROLLER
+   help
+ Add support for the Synopsys DesignWare watchdog timer.
+
 config WATCHDOG_MXS28
bool "i.MX28"
depends on ARCH_IMX28
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index e3afe1c27efb..5fca4c368c40 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -2,5 +2,6 @@ obj-$(CONFIG_WATCHDOG) += wd_core.o
 obj-$(CONFIG_WATCHDOG_DAVINCI) += davinci_wdt.o
 obj-$(CONFIG_WATCHDOG_OMAP) += omap_wdt.o
 obj-$(CONFIG_WATCHDOG_MXS28) += im28wd.o
+obj-$(CONFIG_WATCHDOG_DW) += dw_wdt.o
 obj-$(CONFIG_WATCHDOG_JZ4740) += jz4740.o
 obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o
diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
new file mode 100644
index ..6de2b84356dc
--- /dev/null
+++ b/drivers/watchdog/dw_wdt.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2010-2011 Picochip Ltd., Jamie Iles
+ * http://www.picochip.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This file implements a driver for the Synopsys DesignWare watchdog device
+ * in the many subsystems. The watchdog has 16 different timeout periods
+ * and these are a function of the input clock frequency.
+ *
+ * The DesignWare watchdog cannot be stopped once it has been started so we
+ * do not implement a stop function. The watchdog core will continue to send
+ * heartbeat requests after the watchdog device has been closed.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define WDOG_CONTROL_REG_OFFSET0x00
+#define WDOG_CONTROL_REG_WDT_EN_MASK   0x01
+#define WDOG_TIMEOUT_RANGE_REG_OFFSET  0x04
+#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT4
+#define WDOG_CURRENT_COUNT_REG_OFFSET  0x08
+#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
+#define WDOG_COUNTER_RESTART_KICK_VALUE0x76
+
+/* The maximum TOP (timeout period) value that can be set in the watchdog. */
+#define DW_WDT_MAX_TOP 15
+
+#define DW_WDT_DEFAULT_SECONDS 30
+
+struct dw_wdt {
+   void __iomem*regs;
+   struct clk  *clk;
+   struct restart_handler  restart;
+   struct watchdog wdd;
+   struct reset_control*rst;
+};
+
+#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
+
+static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
+{
+   /*
+* There are 16 possible timeout values in 0..15 where the number of
+* cycles is 2 ^ (16 + i) and the watchdog counts down.
+*/
+   return (1U << (16 + top)) / clk_get_rate(dw_wdt->clk);
+}
+
+static int dw_wdt_start(struct watchdog *wdd)
+{
+   struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
+
+   writel(WDOG_CONTROL_REG_WDT_EN_MASK,
+  dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
+
+   return 0;
+}
+
+static int dw_wdt_stop(struct watchdog *wdd)
+{
+   struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
+
+   if (IS_ERR(dw_wdt->rst)) {
+   dev_warn(dw_wdt->dev, "No reset line. Will not stop.\n");
+   return PTR_ERR(dw_wdt->rst);
+   }
+
+   reset_control_assert(dw_wdt->rst);
+   reset_control_deassert(dw_wdt->rst);
+
+   return 0;
+}
+
+static int dw_wdt_set_timeout(struct watchdog *wdd, unsigned int top_s)
+{
+   struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
+   int i, top_val = DW_WDT_MAX_TOP;
+
+   if (top_s == 0)
+   return dw_wdt_stop(wdd);
+
+   /*
+* Iterate over the timeout values until we find the closest match. We
+* always look for >=.
+*/
+   for (i = 0; i <= DW_WDT_MAX_TOP; ++i) {
+   if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
+   top_val = i;
+   break;
+   }
+   }
+
+   /*
+* Set the new value in the watchdog.  Some versions of dw_wdt
+* have have TOPINIT in the TIMEOUT_RANGE register (as per
+* 

[PATCH v2 1/3] reset: import socfpga-reset driver from linux

[Steffen Trumtrar]

Port the linux v4.8-rc1 reset-socfpga driver to barebox.

Signed-off-by: Steffen Trumtrar 
---
Changes since v1:
  - use dev_request_mem_resource

 drivers/reset/Makefile|   1 +
 drivers/reset/reset-socfpga.c | 124 ++
 2 files changed, 125 insertions(+)
 create mode 100644 drivers/reset/reset-socfpga.c

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f2b995..52b10cd48055 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_RESET_CONTROLLER) += core.o
+obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index ..9214197e627d
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2014 Steffen Trumtrar 
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NR_BANKS   4
+
+struct socfpga_reset_data {
+   spinlock_t  lock;
+   void __iomem*membase;
+   u32 modrst_offset;
+   struct reset_controller_dev rcdev;
+};
+
+static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   struct socfpga_reset_data *data = container_of(rcdev,
+struct socfpga_reset_data,
+rcdev);
+   int bank = id / BITS_PER_LONG;
+   int offset = id % BITS_PER_LONG;
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg | BIT(offset), data->membase + data->modrst_offset +
+(bank * NR_BANKS));
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct socfpga_reset_data *data = container_of(rcdev,
+struct socfpga_reset_data,
+rcdev);
+
+   int bank = id / BITS_PER_LONG;
+   int offset = id % BITS_PER_LONG;
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+
+   reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+   writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
+ (bank * NR_BANKS));
+
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
+static struct reset_control_ops socfpga_reset_ops = {
+   .assert = socfpga_reset_assert,
+   .deassert   = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct device_d *dev)
+{
+   struct socfpga_reset_data *data;
+   struct resource *res;
+   struct device_node *np = dev->device_node;
+
+   data = xzalloc(sizeof(*data));
+
+   res = dev_request_mem_resource(dev, 0);
+   data->membase = IOMEM(res->start);
+   if (IS_ERR(data->membase))
+   return PTR_ERR(data->membase);
+
+   if (of_property_read_u32(np, "altr,modrst-offset", 
>modrst_offset)) {
+   dev_warn(dev, "missing altr,modrst-offset property, assuming 
0x10!\n");
+   data->modrst_offset = 0x10;
+   }
+
+   spin_lock_init(>lock);
+
+   data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
+   data->rcdev.ops = _reset_ops;
+   data->rcdev.of_node = np;
+
+   return reset_controller_register(>rcdev);
+}
+
+static const struct of_device_id socfpga_reset_dt_ids[] = {
+   { .compatible = "altr,rst-mgr", },
+   { /* sentinel */ },
+};
+
+static struct driver_d socfpga_reset_driver = {
+   .probe  = socfpga_reset_probe,
+   .of_compatible  = DRV_OF_COMPAT(socfpga_reset_dt_ids),
+};
+
+static int socfpga_reset_init(void)
+{
+   return platform_driver_register(_reset_driver);
+}
+postcore_initcall(socfpga_reset_init);
-- 
2.9.3


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