From: Christian Hemp <c.h...@phytec.de>
Sync the USDCH drive strength muxing with kernel.
With this drive strength we saw no sd card errors.
Signed-off-by: Christian Hemp <c.h...@phytec.de>
Acked-by: Stefan Lengfeld <s.lengf...@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmuel...@phytec.de>
Signed-off-by: Christian Hemp <c.h...@phytec.de>
---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 3a5b0dbf24..923c79c67b 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -205,12 +205,12 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31
0x80000000 /* CD */
>;
};
--
2.16.1
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