On Mon, Jul 5, 2021 at 1:14 AM Grant Likely wrote:
>
> On 23/06/2021 07:34, Atish Patra wrote:
> > On Tue, Jun 22, 2021 at 7:54 AM Grant Likely wrote:
> > Regarding "UEFI Boot at S mode" section [1], it just tries to
> > emphasize that UEFI boot at S-mo
On Tue, Jun 22, 2021 at 7:54 AM Grant Likely wrote:
>
> On 22/06/2021 15:05, Matthias Brugger wrote:
> >
> >
> > On 22/06/2021 15:18, Grant Likely wrote:
> >> On 22/06/2021 11:50, Daniel Thompson wrote:
> >>> On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
>
>
> On
On Mon, Jun 21, 2021 at 1:53 PM Grant Likely wrote:
>
>
>
> On 21/06/2021 18:35, Atish Patra wrote:
> > On Mon, Jun 21, 2021 at 10:19 AM Grant Likely wrote:
> >>
> >>
> >>
> >> On 10/05/2021 18:37, Atish P
On Mon, Jun 21, 2021 at 10:19 AM Grant Likely wrote:
>
>
>
> On 10/05/2021 18:37, Atish Patra wrote:
> > This patch adds all the required content to make RISC-V EBBR compatible.
> > The additional content is not a lot given that we just need to update the
> > arch
On Mon, May 10, 2021 at 10:37 AM Atish Patra wrote:
>
> This patch adds all the required content to make RISC-V EBBR compatible.
> The additional content is not a lot given that we just need to update the
> architecture specific sections for RISC-V. Rest of the document is ISA
This patch adds all the required content to make RISC-V EBBR compatible.
The additional content is not a lot given that we just need to update the
architecture specific sections for RISC-V. Rest of the document is ISA agnostic
anyways.
Signed-off-by: Atish Patra
---
source/chapter1-about.rst
On Thu, May 6, 2021 at 2:24 AM Heinrich Schuchardt wrote:
>
> On 06.05.21 09:06, Atish Patra wrote:
> > This patch adds all the required content to make RISC-V EBBR compatible.
> > The additional content is not a lot given that we just need to update the
> > architectu
This patch adds all the required content to make RISC-V EBBR compatible.
The additional content is not a lot given that we just need to update the
architecture specific sections for RISC-V. Rest of the document is ISA agnostic
anyways.
Signed-off-by: Atish Patra
---
source/chapter1-about.rst
t; > -Original Message-
> > From: Chang, Abner (HPS SW/FW Technologist)
> > Sent: Saturday, October 3, 2020 11:24 AM
> > To: Heinrich Schuchardt ; Ard Biesheuvel
> >
> > Cc: Atish Patra ; boot-architecture@lists.linaro.org;
> > Grant Likely ; Rick Ch
On Thu, Oct 22, 2020 at 4:19 PM Atish Patra wrote:
>
> On Wed, Oct 21, 2020 at 3:21 AM Grant Likely wrote:
> >
> > Hi Atish,
> >
> > Thanks for this. Comments below.
> >
> > On 16/10/2020 02:10, Atish Patra wrote:
> > > This patch add
On Wed, Oct 21, 2020 at 3:21 AM Grant Likely wrote:
>
> Hi Atish,
>
> Thanks for this. Comments below.
>
> On 16/10/2020 02:10, Atish Patra wrote:
> > This patch adds all minimum mandatory requirements to make RISC-V compatible
> > with EBBR.
>
On Wed, Oct 21, 2020 at 5:42 AM Grant Likely wrote:
>
> On 13/10/2020 19:39, Atish Patra wrote:
> > Signed-off-by: Atish Patra
>
> No need for this to be a separate patch. Squash into patch 2 please
> where the additional copyright text is actually added.
&g
On Mon, 2020-10-19 at 11:50 +0100, Daniel Thompson wrote:
> On Fri, Oct 16, 2020 at 12:33:07PM -0700, Atish Patra wrote:
> > On Fri, Oct 16, 2020 at 4:29 AM Daniel Thompson
> > wrote:
> > > On Thu, Oct 15, 2020 at 06:10:32PM -0700, Atish Patra wrote:
> > > > +
On Fri, Oct 16, 2020 at 4:29 AM Daniel Thompson
wrote:
>
> On Thu, Oct 15, 2020 at 06:10:32PM -0700, Atish Patra wrote:
> > This patch adds all minimum mandatory requirements to make RISC-V compatible
> > with EBBR.
> >
> > Signed-off-by: Atish Patra
> >
This patch adds all minimum mandatory requirements to make RISC-V compatible
with EBBR.
Signed-off-by: Atish Patra
---
source/chapter1-about.rst | 42 +++--
source/chapter2-uefi.rst| 10 +++-
source/chapter3-secureworld.rst | 14 +++
source
Signed-off-by: Atish Patra
---
source/index.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/source/index.rst b/source/index.rst
index bf2dadf3be47..6758994c5bbf 100644
--- a/source/index.rst
+++ b/source/index.rst
@@ -1,5 +1,6 @@
.. EBBR Source Document
Copyright Arm Limited
.
The series is also available in my github repo.
https://github.com/atishp04/ebbr/tree/riscv_update
Changes from v1->v2:
1. Added ACPI todo list.
2. Removed efistub requirements as that is linux specific.
3. Fix typos.
Atish Patra (2):
Add Western Digital copyright
Add RISC-V support content
On Tue, Oct 13, 2020 at 5:55 PM Heinrich Schuchardt wrote:
>
> Am 14. Oktober 2020 02:13:41 MESZ schrieb Atish Patra :
> >On Tue, Oct 13, 2020 at 4:33 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Am 14. Oktober 2020 01:03:51 MESZ schrieb Atish Patra
> &
On Tue, Oct 13, 2020 at 4:33 PM Heinrich Schuchardt wrote:
>
> Am 14. Oktober 2020 01:03:51 MESZ schrieb Atish Patra :
> >On Tue, Oct 13, 2020 at 3:21 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Am 13. Oktober 2020 20:39:12 MESZ schrieb Atish Patra
> >:
&
On Tue, Oct 13, 2020 at 3:21 PM Heinrich Schuchardt wrote:
>
> Am 13. Oktober 2020 20:39:12 MESZ schrieb Atish Patra :
> >This patch adds all minimum mandatory requirements to make RISC-V
> >compatible
> >with EBBR.
> >
> >Signed-off-by: Atish Patra
This patch adds all minimum mandatory requirements to make RISC-V compatible
with EBBR.
Signed-off-by: Atish Patra
---
source/chapter1-about.rst | 42 +++--
source/chapter2-uefi.rst| 10 +++-
source/chapter3-secureworld.rst | 13 ++
source
Signed-off-by: Atish Patra
---
source/index.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/source/index.rst b/source/index.rst
index bf2dadf3be47..6758994c5bbf 100644
--- a/source/index.rst
+++ b/source/index.rst
@@ -1,5 +1,6 @@
.. EBBR Source Document
Copyright Arm Limited
.
The series is also available in my github repo.
https://github.com/atishp04/ebbr/tree/riscv_update
Atish Patra (2):
Add Western Digital copyright
Add RISC-V support content to the EBBR specification
source/chapter1-about.rst | 42 +++--
source/chapter2-uefi.rst
nologist) ;
> > boot-architecture@lists.linaro.org; Atish Patra
> > Cc: Rick Chen ; Atish Patra ;
> > Grant Likely ; Ard Biesheuvel
> > Subject: Re: EBBR: RISC-V handoff to OS
> >
> > On 9/23/20 7:24 AM, Chang, Abner (HPS SW/FW Technologist) wrote:
> >
On Mon, Sep 21, 2020 at 6:11 PM Chang, Abner (HPS SW/FW Technologist)
wrote:
>
>
>
> > -Original Message-
> > From: Atish Patra [mailto:ati...@atishpatra.org]
> > Sent: Tuesday, September 22, 2020 2:28 AM
> > To: Heinrich Schuchardt
> &
On Mon, Sep 21, 2020 at 9:23 AM Heinrich Schuchardt wrote:
>
> Hello Atish,
>
> the UEFI spec has this sentence:
>
> "When UEFI firmware handoff control to OS, the RISC-V is operated in
> machine-mode privilege." (M-mode is the equivalent to EL3 in ARM).
>
> This does not make any sense to me when
On Thu, 2020-09-17 at 03:24 +0200, Heinrich Schuchardt wrote:
> On 9/16/20 7:27 PM, Atish Patra wrote:
> > On Wed, Sep 16, 2020 at 9:04 AM François Ozog <
> > francois.o...@linaro.org> wrote:
> > > Hi Atish,
> > >
> > > Is the HARTID in DT used t
On Wed, Sep 16, 2020 at 9:04 AM François Ozog wrote:
>
> Hi Atish,
>
> Is the HARTID in DT used to *define* which thread should used as the
> booted payload (Linux) or is it used to *inform* Linux that it was
> started on this particular HARTID?
>
The latter. It is just to inform EFI stub that bo
On Thu, Aug 20, 2020 at 1:40 PM Heinrich Schuchardt wrote:
>
> On 8/20/20 10:09 PM, Atish Patra wrote:
> > On Thu, Aug 20, 2020 at 1:03 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On 8/20/20 9:32 PM, Atish Patra wrote:
> >>> +Paul
> >
On Thu, Aug 20, 2020 at 1:03 PM Heinrich Schuchardt wrote:
>
> On 8/20/20 9:32 PM, Atish Patra wrote:
> > +Paul
> >
> > On Thu, Aug 20, 2020 at 8:46 AM Grant Likely > <mailto:grant.lik...@arm.com>> wrote:
> >
> > Hi Atish,
> >
>
On Thu, Aug 20, 2020 at 12:39 PM Heinrich Schuchardt
wrote:
> On 8/20/20 8:10 PM, Atish Patra wrote:
> >
> >
> > On Thu, Aug 20, 2020 at 10:35 AM Heinrich Schuchardt > <mailto:xypron.g...@gmx.de>> wrote:
> >
> > On 8/20/20 6:45 PM, D
>
> g.
>
> On 20/08/2020 01:03, Atish Patra wrote:
> > Hi All,
> > We are interested in adopting EBBR as the boot specification for the
> > embedded RISC-V platforms.
> > We firmly believe that EBBR is a very well defined specification for
> > boot requirement
On Thu, Aug 20, 2020 at 1:45 AM Heinrich Schuchardt
wrote:
> On 20.08.20 08:45, Ard Biesheuvel wrote:
> > (+ Grant, Francois)
> >
> > On Thu, 20 Aug 2020 at 02:04, Atish Patra wrote:
> >>
> >> Hi All,
> >> We are interested in adopting EBBR as the
7;m happy to add RISC-V content to EBBR. EBBR was originated as a
> >> community driven document, and though it was created to solve problems
> >> in the Arm ecosystem, it is not limited to Arm platforms.
> >>
> >> g.
> >>
> >> On 20/08/2020 01:03, Atish Patr
Hi All,
We are interested in adopting EBBR as the boot specification for the
embedded RISC-V platforms.
We firmly believe that EBBR is a very well defined specification for
boot requirement and there
is no need for reinventing the wheel for RISC-V. Hence, this is a
thread to discuss all the require
35 matches
Mail list logo
