Re: [casper] How to make a muti-clock design with roach?

With ADCs in the design, I can use the adcX_clk, while I want to use a clock a little higher than adcX_clk to process with the data. How can I deal with the second clock? The short answer is that you can't. Simulink can create a fake 2x clock for you by adding enable/clock gating lines to

Re: [casper] Roach1 CX4 port to reference xtal mapping

Hi Matt I have, for ROACH-1: X1: CX-0 maps to MGT bottom 0 CX-1 maps to MGT bottom 1 X4: CX-2 maps to MGT top 0 CX-3 maps to MGT top 1 Jason On 07 Apr 2012, at 03:46, Matt Dexter wrote: Hi, I've confused myself when I try to map CX4 port to reference crystal - I hope one of you can

[casper] Fwd: Roach1 CX4 port to reference xtal mapping

Oops, sorry, I think I've just confused myself and mis-informed you in the process. Having checked the schematics, it seems... X1 drives MGT_REFCLK_Q1_1 and MGT_REFCLK_Q1_3 (ie ports 1 and 3) through buffer U8, both going in to FPGA. X4 drives MGT_REFCLK_Q2_0 and MGT_REFCLK_Q2_2 (ie ports 0 and

Re: [casper] Fwd: Roach1 CX4 port to reference xtal mapping

Thanks Henno and Jason, It was just this cross-mapping vs use in software that was getting me confused. Relieved to have your input. Matt On Tue, 10 Apr 2012, Henno Kriel wrote: Hi Jason I have checked the clocking and agree. Henno On Tue, Apr 10, 2012 at 1:06 PM, Jason Manley