Hi Nilan, I think the problem is that your design appears (based on the timing report) to require a signal to propagate from the output of “delay42” through “convert8” through “mult2” through “addsub1" through “addsub2" and through “mult1” all within one clock cycle. That is simply asking too much from the FPGA. As the timing report indicates, “Component delays alone exceed the constraint”, which means that the timing constraint could not be met even if the signal had zero propagation delay between components. You somehow have to restructure the filter implementation so that it can be realized within the limits of the FPGA. You might be able to gain some improvements through clever use of the DSP48 block in Matlab, which can provide more control of DSP48 blocks rather than relying on the tools to merge multipliers and adders in an optimal way, but I suspect that alone will not be sufficient to get this design to meet timing. I also suspect that the bit width of the signal is rather large as well, which also makes things harder.
Hope this helps, Dave On Mar 10, 2016, at 16:49, Nilan Udayanga <g...@zips.uakron.edu <mailto:g...@zips.uakron.edu>> wrote: > Hi Jack, > > Thank you very much for your suggestions. The block t_z2 is a 2nd order > feedback loop (figure is attached, Even though it shows 3 delays in > multipliers, it does not have any delays). > But I don't think this feedback loop may cause that much of delay. > > Regards, > Nilan Udayanga. > > On Thu, Mar 10, 2016 at 7:18 PM, Jack Hickish <jackhick...@gmail.com > <mailto:jackhick...@gmail.com>> wrote: > Hi Nilan, > > It looks like there's a block called (something like) ppcm12/block_t_z2 with > a huge logic delay -- from line 135 of the failing twr file -- > > Data Path Delay: 20.585ns (Levels of Logic = 12)(Component delays > alone exceeds constraint) > > What is this block? It looks like it has some multipliers and adders and > stuff... > > There's also a timing error in the adc yellow block, but my guess is this is > just because the place and route tool gave up when it hit impossible > constraints elsewhere. > > Cheers, > Jack > > On Thu, 10 Mar 2016 at 23:49 Nilan Udayanga <g...@zips.uakron.edu > <mailto:g...@zips.uakron.edu>> wrote: > Hi all, > > We are having a little weird problem during the compilation of a roach 2 > design with the adc16 block. I have a design for a specific application. It > is well pipelined and we are using ADC interfaces clocked at 200 MHz. When I > just terminate the output without using any software registers at the output, > there is no timing error (all timing costrains have been met). And when I > compile the design using the software register at the output (just a one > software register), it has a timing error, and says the maximum frequency > that can be achieved is around 50 MHz. I am wondering whether it is a problem > with the software register or not. Please find the following attachments for > the .twr and .twx files for each cases. > > I have tried using snapshots blocks too. Thats giving the same timing error. > > Your help will be greatly appreciated. > > Regards, > Nilan Udayanga. > > On Wed, Mar 9, 2016 at 4:03 PM, Nilan Udayanga <g...@zips.uakron.edu > <mailto:g...@zips.uakron.edu>> wrote: > Hi All, > > Thank you very much for all your suggestions. > > I have two more questions, > > Since, ADCs need to be clocked at 480 MHz for the demux=2 mode, how does the > FPGA clock at 240 MHz? does it use a clock divider internally? > > Is there any maximum operating frequency for the FPGA, when we use the adc16 > block? > > Regards, > Nilan Udayanga. > > On Wed, Mar 9, 2016 at 3:22 PM, Jack Hickish <jackhick...@gmail.com > <mailto:jackhick...@gmail.com>> wrote: > With regards to the demux option, for the system you describe you want -d 2 > (I.e. demux by = run the FPGA at half the sample rate, and process two > samples in parallel on every FPGA clock cycle). Basically, provided you have > the up to date ruby package, all you need to do is run adc16_init.rb with > appropriate options, and that will program your roach and set everything up > for you. > > I think the default mode of the adc16 ruby script assumes that, whatever mode > you're using the ADC in, the external clock provided is at the sample rate. > Though, as Matt added, the ADC supports other dividing options if they're > useful to you and you're willing to read the ADC data sheet to work out how > to set the divider properties. > > Cheers > Jack > > > On Wed, 9 Mar 2016, 09:49 David MacMahon, <dav...@astro.berkeley.edu > <mailto:dav...@astro.berkeley.edu>> wrote: > Hi Vishwa, > > I am not at my computer right now, so this is from memory, but I think you > want to specify an IP clock rate of 240 MHz and supply a 480 MHz clock to the > ADC card(s). The IP clock rate is sometimes called the fabric clock rate. It > is the rate at which the FPGA logic elements (aka fabric) operate. The ADC > chips need a sample clock that is commensurate with the sampling frequency. > When you initialize the ADCs using adc16_init.rb, be sure to pass the "-d" > option. If your version of adc16_init.rb does not support the "-d" option, > then you will need to update it. > > Hope this helps, > Dave > > On Mar 9, 2016, at 08:33, Vishwa Seneviratne <mp...@zips.uakron.edu > <mailto:mp...@zips.uakron.edu>> wrote: > >> Hi David/Jack, >> >> We are working on a beam former and we use the 'ADC16x250-8 coax rev 2' to >> sample RF signals using ROACH2-Rev 2. The operating BW is 240MHz. Thus, we >> need to sample the signals at 480 MSamples/s. We have few queries regarding >> the adc16 yellow block and how to setup the input clock. >> >> 1. Can we compile a design by setting the IP clock rate to 480MHz? >> 2. Should we supply a IP clock frequency of 480MHz to the ADC board to >> achieve a sampling rate of 480MSamples/s. If not, at what clock rate should >> we supply? And what other parameters needed to setup when running the bof >> file. >> >> Thank you >> >> >> Sincerely, >> >> Vishwa Seneviratne >> Graduate Student >> Dept. of Electrical and Computer Engineering >> University of Akron >> >> On Wed, Feb 3, 2016 at 12:38 PM, David MacMahon <dav...@astro.berkeley.edu >> <mailto:dav...@astro.berkeley.edu>> wrote: >> Hi, Vishwa, >> >> The software installed by following the ADC16 user guide had not been >> updated with the newer version of the adc16 code that supports demux mode. >> I have updated the software that the user guide points to, so if you >> reinstall the adc16 gem as per the user guide you should get version 0.4.0 >> which supports demux mode. >> >> Thanks for bringing this issue to my attention. >> >> Dave >> >>> On Feb 3, 2016, at 7:02 PM, Vishwa Seneviratne <mp...@zips.uakron.edu >>> <mailto:mp...@zips.uakron.edu>> wrote: >>> >>> Hi Dave, >>> >>> Here is the output. >>> >>> vishwa@server3:~/Desktop/roach/poly$ adc16_init.rb -h >>> Usage: adc16_init.rb [OPTIONS] HOSTNAME BOF >>> >>> Programs HOSTNAME with ADC16-based design BOF and then calibrates >>> the serdes receivers. >>> >>> Options: >>> -i, --iters=N Number of snaps per tap [1] >>> -r, --reg=R1=V1[,R2=V2...] Register addr=value pairs to set >>> -v, --[no-]verbose Display more info [false] >>> -h, --help Show this message >>> >>> vishwa@server3:~/Desktop/roach/poly$ gem list adc16 >>> >>> *** LOCAL GEMS *** >>> >>> adc16 (0.3.6) >>> >>> >>> >>> >>> Sincerely, >>> >>> Vishwa Seneviratne >>> Graduate Student >>> Dept. of Electrical and Computer Engineering >>> University of Akron >>> >>> On Wed, Feb 3, 2016 at 11:28 AM, David MacMahon <dav...@astro.berkeley.edu >>> <mailto:dav...@astro.berkeley.edu>> wrote: >>> What does "adc16_init.rb -h" show? What does "gem list adc16" show? Maybe >>> you need a newer version of the adc16 code. >>> >>> Dave >>> >>> On Feb 3, 2016, at 18:20, Vishwa Seneviratne <mp...@zips.uakron.edu >>> <mailto:mp...@zips.uakron.edu>> wrote: >>> >>>> Hi Jack, >>>> >>>> I'm thinking that the ruby script 'adc16_init.rb' does not identify the >>>> '--demux' parameter. I used the code at >>>> 'git://github.com/david-macmahon/casper_adc16.git >>>> <http://github.com/david-macmahon/casper_adc16.git>'. What can I do to set >>>> the parameter? >>>> >>>> Thank you >>>> >>>> >>>> Sincerely, >>>> >>>> Vishwa Seneviratne >>>> Graduate Student >>>> Dept. of Electrical and Computer Engineering >>>> University of Akron >>>> >>>> On Wed, Feb 3, 2016 at 11:02 AM, Vishwa Seneviratne <mp...@zips.uakron.edu >>>> <mailto:mp...@zips.uakron.edu>> wrote: >>>> Hi Jack, >>>> >>>> I did try all the combinations. The error remains the same. >>>> >>>> $ adc16_init.rb -v --demux=1 192.168.10.5 poly_design.bof >>>> /var/lib/gems/1.9.1/gems/adc16-0.3.6/bin/adc16_init.rb:40:in `<top >>>> (required)>': invalid option: --demux=2 (OptionParser::InvalidOption) >>>> from /usr/local/bin/adc16_init.rb:19:in `load' >>>> from /usr/local/bin/adc16_init.rb:19:in `<main>' >>>> >>>> >>>> Sincerely, >>>> >>>> Vishwa Seneviratne >>>> Graduate Student >>>> Dept. of Electrical and Computer Engineering >>>> University of Akron >>>> >>>> On Wed, Feb 3, 2016 at 2:25 AM, Jack Hickish <jackhick...@gmail.com >>>> <mailto:jackhick...@gmail.com>> wrote: >>>> Hi Vishwa, >>>> >>>> Is the syntax definitely -demux=1 andnot either --demux=1 or -d 1 ? >>>> >>>> >>>> >>>> Jack >>>> >>>> >>>> On Wed, 3 Feb 2016, 12:39 a.m. Vishwa Seneviratne <mp...@zips.uakron.edu >>>> <mailto:mp...@zips.uakron.edu>> wrote: >>>> Hi, >>>> >>>> I am working on how to work with different operating of the 'ADC16x250-8 >>>> coax rev 2' for a very simple design to test how the ADC works. The design >>>> is compiled at an IP clock rate setting of 200MHz. My objective is to >>>> sample my input signal at higher sampling rate (preferably 400, 800 MHz). >>>> >>>> According to the user guide >>>> ''https://casper.berkeley.edu/wiki/images/4/4c/ADC16_user_guide.txt >>>> <https://casper.berkeley.edu/wiki/images/4/4c/ADC16_user_guide.txt>" by >>>> setting the demux parameter I should be able to switch between different >>>> sampling rates. I get the following error. >>>> >>>> $ adc16_init.rb -v -demux=1 192.168.10.5 poly_design.bof >>>> /var/lib/gems/1.9.1/gems/adc16-0.3.6/bin/adc16_init.rb:40:in `<top >>>> (required)>': invalid option: -demux=2 (OptionParser::InvalidOption) >>>> from /usr/local/bin/adc16_init.rb:19:in `load' >>>> from /usr/local/bin/adc16_init.rb:19:in `<main>' >>>> >>>> When I don't pass the 'demux' parameter the ADC board get initialized to 8 >>>> analog inputs by default. >>>> >>>> How do I resolve this issue? or how can I set the ADC's to operate at >>>> different sampling rates? >>>> >>>> Thank you in advance >>>> >>>> Sincerely, >>>> >>>> Vishwa Seneviratne >>>> Graduate Student >>>> Dept. of Electrical and Computer Engineering >>>> University of Akron >>>> >>>> >>> >> >> > > > > <Screenshot 2016-03-10 19.43.14.png>
