Hi Adam,
I will go through what I did to get the Skarab into this state.
import casperfpga
fpga = casperfpga.SkarabFpga('169.254.128.213')
fpga.convert_hex_to_bin('frm123701u1r1_mez3_golden_ska_sa.hex',True);
fpga.convert_hex_to_bin('frm123701u1r1_mez3_ska_sa.hex',True);
fpga.virtex_flash_reconfi
Hi Jonathan,
Thanks for the feedback on the documents and your kind words. These
documents will be added to a repo and linked to the wiki by the end of next
week. I will send an email out when this is ready.
I agree with Clifford. I am still not sure what caused the board to be
bricked and I thin
Hello Clifford,
Thank you very much for the detailed response, and it is good to know Peralex
is overlooking the correspondence. I confess to being a little frustrated at
the end of the day yesterday, so may have been a bit grumpy. Adam bore the
brunt, and I really do appreciate his patient, g
Hi Jonathan (and Adam/Wesley/Mark)
*Firstly*, I want to assure you that Peralex is monitoring the Casper
group mails, and we will step in where we feel it necessary. Right now,
it looks like you are getting excellent support from SKA-SA.
*Secondly*, our aim with Skarab is that end users never pop
Thanks very much for the quick response, Adam, and the detailed procedures,
much appreciated. I found two JTAG pods, one the Xilinx branded one, and a
more compact version by Diligent, and a couple of cable sets. An attempt at
reprogramming will be made today and we will let you know. Best re
Hi Jonathan and Mark,
I have written a How To for configuring the flash via the JTAG (
https://docs.google.com/a/ska.ac.za/document/d/1TeVELJ1jEQLzk-qqzWhXODd_HEalTkDJhXq4Q1Y_qgU/edit?usp=sharing
)
I have also updated the https://github.com/ska-sa/skarab_bsp_images (master
branch) repo with the *
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