Hi Dan, that's great information - very helpful.many thanks, best wishes
NeilSent from my Galaxy
Original message From: Dan Werthimer
Date: 11/11/2023 21:51 (GMT+00:00) To: casper@lists.berkeley.edu Subject: Re:
[casper] state of the art single bit correlators hi neil, i don'
hi neil,
i don't think waiting 5 years will help:
there will be faster serdes - the current chips handle ~5 Tbit/sec and that
will probably double every two years,
but that won't help you because you need other fpga's to convert your slow
1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.
hi neil,
regarding how big an FPGA you need:
let's assume 512 complex signals at 1 Gbit/sec real, 1 Gbit/sec imag:
you'll need ~512^2 / 2 = 2^17 complex multipliers, which can be made from
2^18 four bit look up tables, assuming a 500 MHz FPGA clock.
for the accumulators, you need 2^18 adders, 2
Hi Dan,
Those are attractive looking numbers.
Is it possible to say how that might scale over the next 5-years, will the
number of pins go up, faster than the processing speed, or the number of gate
on board? Is it likely to remain I/O bound of compute bound?
Many thanks,
Neil
hi neil,
for a single frequency channel correlator (continuum correlator), an XF
architecture (lag correlator) is the way to go,
the number of antennas in your correlator will likely be limited by the
number of signals you can get into the FPGA.
(the correlator will be I/O bound, not compute bound
Many thanks Dan, cheers, Neil
From: salmon.na via casper@lists.berkeley.edu
Sent: 11 November 2023 20:43
To: casper@lists.berkeley.edu
Subject: RE: [casper] state of the art single bit correlators
Thanks Dan,
Yes, one antenna for one receiver, and there is only one frequency channel,
Thanks Dan,
Yes, one antenna for one receiver, and there is only one frequency channel, and
a single polarisation, so quite a simple configuration.
A good idea to use differential inputs as single bit ADCs.
So the FX correlator looks the better architecture.
So are you saying the
hi niel,
oops, i just re-read your email and my undestanding is that you are
digitizing complex IQ data at 1 Gsps for I and 1 Gsps for Q (1 GHz
bandwidth).
so please cut my numbers in my email from a few minutes ago (appended
below) in half:
you can get ~512 signals digitized (or brought in from
hi neil,
by number of receiver channels, i presume you mean number of antennas?
are these single or dual polarization?
how many spectral channels do you need in your correlator ?
for a large number of spectral channels,
you'll likely want to use an FX architecture correlator (not XF).
in an FX c
Hi Neil,
For your 1-bit correlation, are you going to implement a lag correlator?
If so, then your logic could be:
* ISERDES operating at 1Gbps sampling the complex-valued baseband
* 4-bits at 250MHz or 8-bits at 125MHz inside the FPGA
* Logic to perform 4-bits or 8-bits digital dela
For a paper on non-radioastronomy aperture synthesis technology I need to
know how many receiver channels can run into an almost top of the range FPGA
optimally designed single-bit cross-correlator running a 2 Gbps. So each
receiver is digitised (sine and cosine) in single bits 1 Gbps. I'm wonderin
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