Re: [casper] Split pipelined/direct FFT math

Here's some stuff I wrote up while I was trying to figure out Aaron's FFT magic which might be useful to others. Read at your own risk of course. http://www.eecs.berkeley.edu/~sgowda/parallel_fft_algorithm.pdf -Suraj On Mon, Jun 23, 2014 at 11:43 AM, Aaron Parsons apars...@astron.berkeley.edu

Re: [casper] number of coefficients needed in PFB and FFT

Hi all, The memory footprint of the fft_direct block could be reduced if it is split into two blocks, one for the operator to manipulate the phase of the FFT of each input and another block to calculate the true direct-form FFT, i.e. not mapping together a larger FFT (see p. 615 of

[casper] roach2 bof file problems

Hi all, Does anyone know what causes the error 'cannot execute binary file' when trying to execute a bof file from the powerpc shell? This error occurs with all bof files, including the test designs from github Thanks Suraj

[casper] adc083000 on ROACH2

Hi everyone, Does anyone have a ROACH2-compatible pcore for the adc083000? The auto-update of the clock manager from DCM to MMCM doesn't seem to work properly. I remember discussing this issue before but I can't remember if it was ever resolved. Thanks, Suraj

Re: [casper] Accessing SMA clock inputs and DCM?

If I remember correctly, the SMA inputs are not normally run through a DCM, they're just IO pins (I could be wrong about this..). Specifics on how to make a yellow block are on the wiki: https://casper.berkeley.edu/wiki/How_to_make_a_yellow_ block. Assuming your block is named 'newblock': 0)

Re: [casper] The results of your email commands

Using DSP48s with for addition with a latency of 2 yields the best timing performance, from experience and Xilinx's recommendations, which is why it's hard-coded. -Suraj On Thu, Jul 28, 2011 at 11:53 AM, Samuel Tun samuel@gmail.com wrote: Yes, unchecking the DSP48 adders allows me to change

Re: [casper] Help: MPD not found

Hi Kim, The MPD, BBD, and PAO files should go in mlib_devel/xps_lib/XPS_ROACH_base/pcores/adc_iserdes_1_00_a/ data/ If you're re-compiling from MATLAB, make sure to re-copy the base system. If this can be clarified on the Wiki page instructions, let me know -Suraj On Apr 13, 2011, at 4:46

Re: casper-scm more xBlock stuff

Sorry for the response delay, I've been on a hacker-induced hiatus from Simulink. On Mar 25, 2011, at 6:23 AM, Andrew Martens wrote: Hi all I have read the bit of documentation available on the xBlock interface, looked at some of the scripts, and tried to debug an xBlock problem. It

casper-scm Distributing code for V5 optimized PFB

Hi all, I've developed a PFB FIR real optimized for V5, making the (now usual) modification of directly instantiating dsp48s to use the same multipliers and adders. The problem is that this particular optimization requires eliminating the tap block in the PFB and doing all the

Re: [casper] library update breaks links

Hi Sam, This might be a case where Simulink doesn't find the library. Are the libraries visible in the Simulink LIbrary browser? if they are, try pulling any block from the CASPER DSP blockset into your design, minimize the .mdl and then re-examine it. Are the links still broken after

[casper] Measuring ROACH power dissipation

Hi all, Does the ROACH come with a convenient way of measuring power dissipation? -Suraj

casper-scm FFT Updates

Hi all, In push eb52771 (I think, I'm still pretty bad with git...), I rewrote the fft_wideband_real_init.m script to draw pipeline delays inside the FFT, for the inputs to the biplex cores and between the fft_direct block. I also added a script init_planahead.tcl to

Re: [casper] 3 Gs/s adc board demo example

Hi John, Just to clarify, do you mean 1 board with 16 outputs / cycle at half the clock rate? I implemented this feature but I wouldn't recommend using it for serious computation. For operations like FFT, speed is not as much a problem as the number of simultaneous inputs. -Suraj On

Re: [casper] 3 Gs/s adc board demo example

At 3 Gs/s, the FPGA clock rate is 187.5 MHz. Is this in range of the DRAM clock? Maybe you could describe what the output is and/or how it's incorrect? It's been a while since I attempted to use that interface. _Suraj On Sep 29, 2010, at 6:08 PM, John Ford wrote: Hi John, Just to

Re: [casper] bee_xps fails when building tutorial 3 for R oach

Hi Mandana, Your error is not a Simulink error. It seems that Xilinx's synthesizer can't find the distributed RAM block used in the ROM for the FFT unscrambler. Check in the XPS_ROACH_base/implementation for your design and see if you can find the ngc netlists that it mentions. If not, system

Re: [casper] .bof generation problems

...@astro.berkeley.edu wrote: On Jul 27, 2010, at 10:33 , Suraj Gowda wrote: When I try to run the .bof from the ROACH command line, it returns with Input/Output Error. The ROACH is NFS mounted and I put the bof in the filesystem via scp. Sounds like a corrupted/incomplete bof file. What are its

[casper] FFT drawing issues (wideband real)

Hi casperites, When trying to draw a 16-input real FFT, I get the following error message in 10.1 about 109830498 times: Warning: In instantiating linked block 'spec_256ch_250MHz_clk/fft_wideband_real/fft_direct/butterfly1_5/ twiddle/convert_of2/never' : Xilinx Constant Block Block block

Re: [casper] Fixed FFT block status

Agreed. At the very least, you shouldn't be able to override function names with variable names. 1 point to strongly typed languages... On Jun 24, 2010, at 12:40 PM, Aaron Parsons wrote: FWIW, I've noticed another related problem in the pfb_fir and pfb_fir_real blocks. The mask callbacks

[casper] core_info.tab format

Hello casperites, Does anyone know the format for lines in XPS_ROACH_base/ core_info.tab? All I see is 3 numbers: iadc_controller 321 Thanks, -Suraj

[casper] opb_adccontroller question

Hello casperites, I am looking at the code in opb_adccontroller.vhd and user_logic.vhd. I understand the state machine operation, but the operation seems to depend on the input data Bus2IP_Data, and I'm not seeing where that bus actually changes values. Is it something hidden in

Re: [casper] Basic block upgrade question

Hi Steve, The GUI interface to the block will not change from what you've done unless the mask script dynamically redraws the ports. This may be the case, depending on the block. If not, then deleting readding the block won't do anything to update the ports. You'll have to unlock the

Re: [casper] 6 GS/s Spectrometer

Hi John, I don't think anyone has been able to get a spectrometer working at the full 3GS/s interleaved yet. We are able to digitize and plot raw ADC data at full speed. We run into timing problems when the chip becomes more full, i.e. with an FFT. One possible solution we are (I am)

Re: [casper] CASPER BRAM vector accumulator

Xilinx style fix: Use Glenn's vector accumulator from the GAVRT library. On Apr 7, 2010, at 7:32 AM, Aaron Parsons wrote: It looks like this block is not correctly configured in the library. Volunteers to fix/test? -- Aaron Parsons 510-406-4322 (cell) Campbell Hall 523, UCB

Re: [casper] Which error to chase?

The yellowblocks for the TI DAC part is in xps_library/DACs. I added (but didn't write) the blocks to the main CASPER SVN maybe 2 weeks ago, but did not do any testing as I don't have access to either board. Both blocks are bare bones and contain no simulation interfaces, but they are

[casper] Linux tools keep crashing

Multiple times, after starting a simulation MATLAB will crash and then suddenly nothing from that design will work. So copying the design to a new file and trying to simulate does hangs in the initialization part of the simulation. Anybody else have this problem and/or a solution? I'm

Re: [casper] Linux tools keep crashing

My issue was solved under a different alias. If anyone else has this problem, the thread 'Reference to non-existent field clock_loc' contains a hack. On Feb 16, 2010, at 12:46 AM, Suraj Gowda wrote: Multiple times, after starting a simulation MATLAB will crash and then suddenly nothing

Re: [casper] program ROACH over JTAG

Hello, On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote: Hello All If I want to simulate a design in ISE and generate a bit file to download to ROACH over JTAG. You can do this using the .bit generated by the CASPER toolflow, available in the same location as the .bof. bof files are generated

[casper] Xilinx MAXDELAY constraint compiler bug

, -Suraj Gowda

[casper] KATCP Python Interface doesn't exit cleanly

- opened. Is this a known problem with a solution? Thanks, -Suraj Gowda