Hi John,
I don't think anyone has been able to get a spectrometer working at the full 3GS/s interleaved yet.We are able to digitize and plot raw ADC data at full speed. We run into timing problems when the chip becomes more full, i.e. with an FFT. One possible solution we are (I am) exploring is pre-routing the ADC core (as this is where the router fails). If anyone knows how to pre-route a core for V5 I'd appreciate the help--the Xilinx documentation isn't all that helpful.
-Suraj
