Thanks Dan! Much appreciated!
From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Thursday, April 25, 2019 9:51 AM
To: CASPER Mailing List
Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx transceivers
hi dave,
i don't know about using the SERDES as ADC's.
paul horowitz
st name. Thanks!
>
> -Original Message-
> From: Jack Hickish [mailto:jackhick...@gmail.com]
> Sent: Thursday, April 25, 2019 9:55 AM
> To: casper
> Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx
> transceivers
>
> Hi Dave,
>
> A million years ago (circa
riginal Message-
> From: Jack Hickish [mailto:jackhick...@gmail.com]
> Sent: Thursday, April 25, 2019 9:55 AM
> To: casper
> Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx transceivers
>
> Hi Dave,
>
> A million years ago (circa 2010) Adam Coates (then grad
Jack - you rock - Adam was the name I was recalling, but I could not think of
his last name. Thanks!
-Original Message-
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: Thursday, April 25, 2019 9:55 AM
To: casper
Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx
Hi Dave,
A million years ago (circa 2010) Adam Coates (then grad student of
Prof Mike Jones at Oxford --
https://www2.physics.ox.ac.uk/contacts/people/jonesmi) was looking at
this using ROACH1 (virtex5) transceivers to sample at ~3GHz. IIRC Adam
went into industry after his PhD, and I'm not sure
hi dave,
i don't know about using the SERDES as ADC's.
paul horowitz and andrew howard used the xilinx LVDS inputs as flash ADC
comparators
sampling at about 1 Gsps, they built thousands of multilevel ADC's,
biasing one input of each comparator at different DC levels using a
resistor divider
Hi All,
Has anyone on the CASPER list investigated using the Xilinx transceivers as
1-bit ADCs?
Transceiver receivers can be kept coherent to a reference clock by configuring
the receiver clock-and-data-recovery unit not to recover the clock from the
incoming data stream.
There are some
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