Ok, thanks for the suggestion, I'll try it out.
Franco
On 04/04/17 09:50, James Smith wrote:
Hello Franco,
If you're only using 1 sample at a time, you needn't use a CASPER FFT,
the Xilinx ones do the trick nicely. You can use an asynchronous
1-input PFB if you want to as well.
You would
Hello Franco,
If you're only using 1 sample at a time, you needn't use a CASPER FFT, the
Xilinx ones do the trick nicely. You can use an asynchronous 1-input PFB if
you want to as well.
You would probably need to rework your down-stream stuff though.
Regards,
James
On Tue, Apr 4, 2017 at 2:48
Oh, that may be exactly what I need, I'll try it out.
Thanks!
Franco
On 04/04/17 03:14, Andrew Martens wrote:
Hey Franco
Many of the CASPER blocks were updated a while ago so that you can use
them asynchronously i.e data does not need to be fed to the blocks on
every clock cycle. You can
Hi Jack,
I though of that, but the thing is, if I only take 1 sample per clock
cycle, I'm not sure how to use a 8 input FFT and still keep the same
number of output channels. Maybe I could implement serial-to-parallel
block, and read the FFT every 8 cycles, but I don't know if that's an
Hey Franco
Many of the CASPER blocks were updated a while ago so that you can use them
asynchronously i.e data does not need to be fed to the blocks on every
clock cycle. You can then run your FPGA at a higher clock rate than the
input data rate.
Regards
Andrew
On Tue, Apr 4, 2017 at 4:22 AM,
Hi Franco,
I don't know the low frequency limit, but for what it's worth, you could
always run the adc at 320 MHz and just use 1 of the 8 outputs, which also
has the benefit of avoiding and inter-core mismatch issues, since you'd
effectively only be using 1 core. Or run faster and only use every
Hi All,
I'm working in an application where I need high frequency resolution
(~10kHz). For my model this means I need to run my ADC at ~40MHz (and the
FPGA at 5MHz). I'm not using an special memory block, just brams. I'm using
ROACH2, and ADC5G (https://casper.berkeley.edu/wiki/ADC1x5000-8). It
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