Hi Homin,
Do you have the ability to sniff packets on your DHCP server? Is your
network 1gbe?
If you want you can send me your bitstream and I can run it here to see if
it's a firmware issue or something specific to your network.
Cheers
Jack
On Wed, 16 Jan 2019, 1:21 am Homin Jiang, wrote:
>
Hi Jack:
I modified the vivado version from 2018.2 to 2018.1 in a file under
cont_microblaze. The compilation is fine and completed. Bitcodes are
generated. I have the UART output as following. My problem is the DHCP
i guess. Looks like the DHCP didn't work. Usually, the led right next
to the
On Tue, 15 Jan 2019 at 00:16, Jason Manley wrote:
> This might be a good opportunity for testing partial reconfig, where we
> keep the microblaze up and running during reprogram?!
>
This would make me very happy.
>
> Otherwise, if there's a bit of memory on the board, we could fall-back to
>
es so that we would be able
> to enable the VCU1525 in the same way although using the 40/100G MAC.
>
>
>
> Regards,
>
> BH Hlophe
>
>
>
> *From:* Adam Isaacson
> *Sent:* Tuesday, January 15, 2019 10:17 AM
> *To:* Casper Lists
> *Subject:* Re: [c
This might be a good opportunity for testing partial reconfig, where we keep
the microblaze up and running during reprogram?!
Otherwise, if there's a bit of memory on the board, we could fall-back to the
current SKARAB programming model which uploads a bitstream to off-chip memory,
and then
Hi Jack, Brian and Hong,
Thanks for the excellent work and effort - well done to VCU118 team. The
development team at SARAO are using Matlab 2018a and Vivado 2018.2 for
SKARAB. Further porting effort on this board could be done during the
Hardware Porting Workshop taking place later this year in
Since you asked :)
This incorporates the 1gbe core which Brian got running on the VCU. All I
did was massage the microblaze code we use on SNAP such that it can use
this interface, for its comms. In fact, this is part of a broader attempt
to harmonize the various Ethernet cores Casper provide
jack,
did you do all this work?
hong ?brian ?
dan
On Mon, Jan 14, 2019 at 7:23 PM Jack Hickish wrote:
> Hi CASPERites,
>
> I know a few of you have been playing around with the VCU118 Virtex
> Ultrascale Plus dev board. For a while the toolflow has been able to
> compile designs for
Hi CASPERites,
I know a few of you have been playing around with the VCU118 Virtex
Ultrascale Plus dev board. For a while the toolflow has been able to
compile designs for this board, but without any support for accessing the
software registers / brams in the generated bitstream (making the
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