@postgrad.manchester.ac.uk>, "casper@lists.berkeley.edu"
<casper@lists.berkeley.edu>
主题: Re: Re: [casper] timing errors
Hello Yunpeng,
Black boxing can help speed up compile time but the place-and-route needs to
run every time, so it won't really help the design meet timin
>> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>>
>> -原始邮件-
>> *发件人:*"James Smith" <jsm...@ska.ac.za>
>> *发送时间:*2017-06-04 01:44:39 (星期日)
>> *收件人:* "Michael D'Cruze" <michael.dcr...@postgrad.manchester.ac.uk>
9 (星期日)
> *收件人:* "Michael D'Cruze" <michael.dcr...@postgrad.manchester.ac.uk>
> *抄送:* "门云鹏" <yp...@pku.edu.cn>, "casper@lists.berkeley.edu" <
> casper@lists.berkeley.edu>
> *主题:* Re: [casper] timing errors
>
>
> Hello Yunpeng,
>
> Just
"casper@lists.berkeley.edu"
<casper@lists.berkeley.edu>
主题: Re: [casper] timing errors
Hello Yunpeng,
Just to echo what Michael and Vereese said - those tools can help you get a bit
more insight into what's going on, and how badly your timing problem is, but
the timing rep
ichael
>
>
>
> *From:* 门云鹏 [mailto:yp...@pku.edu.cn]
> *Sent:* 03 June 2017 16:00
> *To:* casper@lists.berkeley.edu
> *Subject:* [casper] timing errors
>
>
>
> Dear all,
>
> I am using ROACH2 to develop digital receiving backend, but I often enco
To: casper@lists.berkeley.edu
Subject: [casper] timing errors
Dear all,
I am using ROACH2 to develop digital receiving backend, but I often encounter
timing errors when I run casper_xps toolflow. I wonder if there is any general
solution to these timing errors.
Thanks a lot,
Yunpeng
Hi Yunpeng,
You can use Xilinx's PlanAead tool to help with the timing errors. You can
place your PFB in a "pblock" which helps with timing. I haven't worked with
this in awhile but there's a tutorial on the CASPER wiki here:
https://casper.berkeley.edu/wiki/Tutorial_PlanAhead
I hope that helps
Dear all,I am using ROACH2 to develop digital receiving backend, but I often
encounter timing errors when I run casper_xps toolflow. I wonder if there is
any general solution to these timing errors.Thanks a lot,Yunpeng
Hi Ryan,
I could get rid of those errors but the tool had hard time in placing
with huge setup timing errors. How much utilization is good to set on
p-blocks ?
Currently, I had 60-70% for different components.
Cheers,
Amit
On 05-Nov-15 9:46 AM, Ryan Monroe wrote:
> Hi Amit,
>
> FYI, I am
Assuming that the pblock is not overlapping with any other pblocks, and
that you have not constrained any other resources in the pblock, I have
used 99% of the resources in a pblock (simply made it as small as
possible). The trouble comes into play when there are resources which
are not in
Hi Amit,
FYI, I am CC'ing the CASPER list on all of these emails, so that they
can be searchable for people in the future.
The placements I gave you were for my personal design, and may not work
for yours. When choosing pblock size, be sure to look at the pblock
utilization in planahead.
np! the 10gbe core wasn't really intended to run at fast clock rates.
Be sure to constrain it to the east-ish side of the chip, this is
probably either a
1. device utilization issue (you are trying to do too much stuff on the
chip), or
2. placement issue (probably this)-- the tools are
Hi Paul,
I believe the placement cost table is the parameter you want to
change (See http://www.xilinx.com/support/answers/35534.html).
You should be able to change this and other compile parameters in
xps_base/XPS_ROACH[2]_base/etc/fast_runtime.opt
You might find that you get on better changing
On 01/30/2014 07:33 AM, Jack Hickish wrote:
Hi Paul,
I believe the placement cost table is the parameter you want to
change (See http://www.xilinx.com/support/answers/35534.html).
You should be able to change this and other compile parameters in
xps_base/XPS_ROACH[2]_base/etc/fast_runtime.opt
I've toyed with Planahead a bit, and quickly found I was in way over my
head. Could you recommend a good starting point for learning this tool?
I'm sure you've found the planahead user guide, which is a bit of a
documentation behemoth, but useful if you have a vague idea of what
setting you're
wow. Thanks a lot Jack!
Paul
On 01/30/2014 10:15 AM, Jack Hickish wrote:
I've toyed with Planahead a bit, and quickly found I was in way over my
head. Could you recommend a good starting point for learning this tool?
I'm sure you've found the planahead user guide, which is a bit of a
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That the subsequent build should contain timing
On 01/29/2014 01:03 PM, Paul Marganian wrote:
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That
On 01/29/2014 01:03 PM, Paul Marganian wrote:
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That
I'm not sure what, if any, difference a subsystem will make to the
mapped design (I thought none), but I believe it's the case that
changing module names etc. can affect the place and route algorithm's
start seed. I seem to remember seeing this mentioned in a Xilinx doc
under the heading I've
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