[casper] fft_wideband_real bug identified and fixed

Hi all, I encountered this issue when I first started to play around with the fft_wideband_real from the CASPER library on Xilinx 14.6 The default bit-width initialization for this block is set at 18_17. However, when we specify the 'word length' as 14 and 'binary point' as 13, in the

Re: [casper] Skewed data samples

On 04/28/2015 04:31 AM, David MacMahon wrote: Have you calculated the skewness for some largish number of samples or are you just going by the appearance of the histogram? If the latter, are you sure that the apparent skewness is not due to artifacts from the histogram bin limits vs discrete

Re: [casper] Skewed data samples

Hi, Tom, Have you calculated the skewness for some largish number of samples or are you just going by the appearance of the histogram? If the latter, are you sure that the apparent skewness is not due to artifacts from the histogram bin limits vs discrete sample values? If you swap ADCs,