[casper] SNAP Board clocking for a low-frequency array

2018-10-19 Thread Nitish Ragoomundun
experience with clocking the SNAP. You see, we run a very tight budget and the M500 LANTIME clock is expensive. We would like to know if there is a less costly way to clock the SNAP and synchronise several boards. Thanks. Best regards, Nitish Ragoomundun Department of Physics University of Mauritius

[casper] Re: SNAP external clock inputs

2018-10-20 Thread Nitish Ragoomundun
've only ever used this output for debugging the synthesizer. I > think python software probably exists to control this output (see > https://github.com/casper-astro/casperfpga/blob/master/src/synth.py) > though I don't know how complete it is. > > Hope that helps a bit, > &g

Re: [casper] SNAP Board clocking for a low-frequency array

2018-10-19 Thread Nitish Ragoomundun
comparing two sources and plotting the > Allen Variance. Be careful of low cost GPSDOs as they are designed for NTP > applications in networks, where 15 ms is all that is required. > > We also have a great deal of experience and hardware (with results) of > using White Rabbit to synch

[casper] SNAP2 with ADC16 board

2018-12-26 Thread Nitish Ragoomundun
Hello everyone, We have a tile of 24 antennas from which we need to acquire data. The central frequency is 327.4 MHz and our working bandwidth is 250 kHz. We need to convert the 24 analogue channels to digital. For this we were thinking about 2x SNAP2 boards operating 12 channels each at 250

Re: [casper] SNAP xdc file

2018-11-29 Thread Nitish Ragoomundun
other CASPER users? > > If you're looking for information on SNAP1 there are schematics at > https://casper.berkeley.edu/wiki/SNAP, and pin configurations in > https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/platforms/snap.yaml > > Cheers > Ja

[casper] SNAP xdc file

2018-11-28 Thread Nitish Ragoomundun
Hello, Does anyone have a .xdc file for the SNAP v2 board? With all the constraints: clocks, pins, buttons, leds and SDRAM? It is essential for our work and we haven't been able to find such a file in the casper-astro repo on GitHub. Regards, Nitish Ragoomundun University of Mauritius -- You

Re: [casper] jasper not working properly after upgrade

2019-11-21 Thread Nitish Ragoomundun
on that >> this is something simple which might have to do with a previous install of >> the title not being overwritten properly. >> >> I'll dig through my notes and get back to you asap >> >> Jack >> >> On Wed, 20 Nov 2019, 12:02 am Nitish Rago

Re: [casper] SNAP ADC at 1GSps

2019-10-18 Thread Nitish Ragoomundun
to read the 3 spectra, each with 2048 complex 64-bit frequency channels, through the Raspberry Pi itself. The connection did choke once, but ran correctly after I changed the cable. Having fun experimenting. ;) Cheers, Nitish On Fri, Oct 11, 2019 at 10:18 PM Nitish Ragoomundun < nitish.ragoo

[casper] SNAP ADC at 1GSps

2019-10-11 Thread Nitish Ragoomundun
Hi, I read from the SNAP wiki page that we can operate the SNAP board ADCs at 1GSps with 3 channels of input. So, I modified the CASPER SNAP tutorial 3 to make the ADC work at 1GSps to obtain a 1 channel spectrometer with a spectrum of 500 MHz. First I modified the SNAP User IP Clock Rate to 250

Re: [casper] SNAP ADC at 1GSps

2019-10-11 Thread Nitish Ragoomundun
around with the adc's clock termination resistors and >> clock distribution chip parameters, >> or use an external dual 1gps zdoc adc. >> >> best wishes, >> >> dan >> >> >> >> >> Dan Werthimer >> Marilyn and Watson Alberts Chair >&

Re: [casper] SNAP FPGA data endianness and networking

2020-08-18 Thread Nitish Ragoomundun
in the 64 > bits unchanged. > > Hopefully that makes sense > > Jack > > > On Tue, 18 Aug 2020 at 13:28, Nitish Ragoomundun < > nitish.ragoomun...@gmail.com> wrote: > >> >> Hello, >> >> We are setting up the digital back-end of a low-fr

[casper] SNAP FPGA data endianness and networking

2020-08-18 Thread Nitish Ragoomundun
Hello, We are setting up the digital back-end of a low-frequency telescope consisting of SNAP boards and GPUs. The SNAP boards packetize the data and send to the GPU processing nodes via 10 GbE links. We are currently programming the packetizer/depacketizer. I have a few questions about the 10gbe

Re: [casper] SNAP FPGA data endianness and networking

2020-08-18 Thread Nitish Ragoomundun
ohl or htohs functions to get it in host format. That way the >>> code stays more portable - if you one day find yourself on a big-endian >>> system, it would work without modification. >>> (https://en.wikipedia.org/wiki/Endianness#Networking) >>> >>> Sometim