> On Sep 23, 2023, at 5:06 PM, Will Cooke via cctalk
> wrote:
>
> I can't answer for Paul, but I can tell you how to do approximate
> calculations for yourself.
>
> You need to know two things: the equivalent parallel resistance (Thevenin
> equivalent) of the two series resistors and
> On 09/23/2023 3:25 PM CDT Warner Losh via cctalk
> wrote:
>
>
> On Sat, Sep 23, 2023, 12:31 PM Paul Koning via cctalk
> wrote:
>
> >
> >
> > > On Sep 22, 2023, at 3:07 PM, Chuck Guzis via cctalk <
> > cctalk@classiccmp.org> wrote:
> > >
> > > On 9/22/23 11:34, emanuel stiebler via
On Sat, Sep 23, 2023, 12:31 PM Paul Koning via cctalk
wrote:
>
>
> > On Sep 22, 2023, at 3:07 PM, Chuck Guzis via cctalk <
> cctalk@classiccmp.org> wrote:
> >
> > On 9/22/23 11:34, emanuel stiebler via cctalk wrote:
> >
> >> There are still some 84pin chips out there(Altera & Xilinx). Sometimes
Paul
A Zynq '30 has 125,000 Logic Cells, a ZU4EG has 192,000 logic cells. Both can
be synthesised with the free tools. You may of course get more LCs on a
supported FPGA, vice SoC.
Logic cell is a marketing term, the engineering equivalent would be "LUT4 +
FF". Google assures me that a
On 2023-09-23 12:36 p.m., Paul Koning via cctalk wrote:
On Sep 22, 2023, at 9:30 PM, Martin Bishop
wrote:
Paul
I endorse your point regarding Lattice's gouging. Support for anything prior to
the XO parts now costs a significant premium. Their XO2 parts are the most useful
to this
> On Sep 22, 2023, at 9:30 PM, Martin Bishop
> wrote:
>
> Paul
>
> I endorse your point regarding Lattice's gouging. Support for anything prior
> to the XO parts now costs a significant premium. Their XO2 parts are the
> most useful to this community - free tools and 0.5 mm pitch, e.g.
> On Sep 22, 2023, at 3:07 PM, Chuck Guzis via cctalk
> wrote:
>
> On 9/22/23 11:34, emanuel stiebler via cctalk wrote:
>
>> There are still some 84pin chips out there(Altera & Xilinx). Sometimes
>> they are pulls, or some 5V tolerant xilinx xc95l
>
> I still have a few 84 pin PLCC
> On Sep 22, 2023, at 9:01 PM, Martin Bishop via cctalk
> wrote:
>
> ...
> Down to 0.5 mm pitch gull wing legs can be readily hand soldered by a
> wireman. Surface mount double sided PCBs can be hand assembled (by me), in
> small quantities, by restricting the components to 0603 and 0.65
Original Message-
From: Mike Katz [mailto:bit...@12bitsbest.com]
Sent: 23 September 2023 01:16
To: General Discussion: On-Topic and Off-Topic Posts
Cc: Martin Bishop
Subject: Re: [cctalk] Re: Good C to FPGA/PLA compiler
Martin,
Thank you for all of your suggestions.
I am a software guy who has dabbled in
On 2023-09-22 20:16, Mike Katz via cctalk wrote:
Martin,
Thank you for all of your suggestions.
Actually, there is something like you're trying to do,
on discord, he is making a board for the data general nova:
uired.
>
> Martin
>
> -Original Message-
> From: Paul Koning [mailto:paulkon...@comcast.net]
> Sent: 23 September 2023 01:46
> To: cctalk@classiccmp.org
> Cc: Martin Bishop
> Subject: Re: [cctalk] Good C to FPGA/PLA compiler
>
>
>
> > On Sep 22, 2023
ired either a dedicated external memory device
or DMA to/fr DRAM would be required.
Martin
-Original Message-
From: Paul Koning [mailto:paulkon...@comcast.net]
Sent: 23 September 2023 01:46
To: cctalk@classiccmp.org
Cc: Martin Bishop
Subject: Re: [cctalk] Good C to FPGA/PLA comp
> On 09/22/2023 6:26 PM CDT Mike Katz via cctalk wrote:
>
>
> I plan on controlling the gate array with an RP2040 dual core cortex M0
> running at 133 MHz and 8 PIO processors.
>
Hi Mike,
Since you are planning to use a micro anyway, and it doesn't appear you will
need a great deal of
> On Sep 22, 2023, at 3:59 PM, Martin Bishop via cctalk
> wrote:
>
> 100% disagree, Verilog and SV are bad tools - very easy to do a bad job with
> - penknife grade.
>
> Verilog however is very c like in that it is untyped and prone to all the
> consequent tar pits; see above.
>
> VHDL
: On-Topic and Off-Topic Posts
Cc: Mike Katz
Subject: [cctalk] Re: Good C to FPGA/PLA compiler
I plan on controlling the gate array with an RP2040 dual core cortex M0 running
at 133 MHz and 8 PIO processors.
However, the Data Break (DMA) timings on the Omnibus are in the 100nS range.
The bus runs
@classiccmp.org]
Sent: 23 September 2023 00:27
To: General Discussion: On-Topic and Off-Topic Posts
Cc: Mike Katz
Subject: [cctalk] Re: Good C to FPGA/PLA compiler
I plan on controlling the gate array with an RP2040 dual core cortex M0 running
at 133 MHz and 8 PIO processors.
However, the Data
via cctalk [mailto:cctalk@classiccmp.org]
Sent: 22 September 2023 23:53
To: ben via cctalk
Cc: Chuck Guzis
Subject: [cctalk] Re: Good C to FPGA/PLA compiler
Stupid question, I know, but someone has to ask it.
Is there some overwhelming reason that the FPGA and associated logic couldn't
I plan on controlling the gate array with an RP2040 dual core cortex M0
running at 133 MHz and 8 PIO processors.
However, the Data Break (DMA) timings on the Omnibus are in the 100nS
range. The bus runs 6 different timing signals plus manipulating all of
the other signals to implement Data
Processor. Jay Jaeger has just elaborated
the UniBone's essentials.
Martin
-Original Message-
From: Chuck Guzis via cctalk [mailto:cctalk@classiccmp.org]
Sent: 22 September 2023 23:53
To: ben via cctalk
Cc: Chuck Guzis
Subject: [cctalk] Re: Good C to FPGA/PLA compiler
Stupid question, I know
On 9/22/2023 4:45 PM, ben via cctalk wrote:
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8).
Stupid question, I know, but someone has to ask it.
Is there some overwhelming reason that the FPGA and associated logic
couldn't be subsumed into an inexpensive 32-bit MCU running at, oh, 200
MHz? I can't believe that a PDP8 is all that fast...
--Chuck
My plan is to have both a serial port for connection to a PC/Terminal
and an I2C output to a multi line display.
Thanks for the suggestion.
On 9/22/2023 4:45 PM, ben via cctalk wrote:
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8). Single Cycle
DMA requires some
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8). Single Cycle
DMA requires some interesting signaling, including putting the
priority on the
On 2023-09-22 12:34 p.m., emanuel stiebler via cctalk wrote:
On 2023-09-22 12:04, Mike Katz via cctalk wrote:
I'm working on the design for an Omnibus (PDP-8/E) debug board and I
am not very good at circuit design. I know there are programs that
will compile something that looks like C into
Mike
The level you are working at, inspecting busses, is not really where C like
tools are targeted - however ...
I shall infer that an 8/E debug board has the functionality of a bus monitor /
logic analyser front end.
The recent discussion <> covered
a lot of similar ground : worth
100% disagree, Verilog and SV are bad tools - very easy to do a bad job with -
penknife grade.
Verilog however is very c like in that it is untyped and prone to all the
consequent tar pits; see above.
VHDL is a good tool which is typed and like the Algol family of languages
precludes many
Oh, and Verilog all the way. I just can't with VHDL.
--
Anders Nelson
www.andersknelson.com
On Fri, Sep 22, 2023 at 3:24 PM Anders Nelson
wrote:
> Maybe these can help?:
>
>
> https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware,
> pair with
>
Maybe these can help?:
https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware,
pair with
https://www.olimex.com/Products/FPGA/iCE40/iCE40-DIO/open-source-hardware
https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
I've personally used the iCE40 and iCE5LP in my
On 9/22/23 11:34, emanuel stiebler via cctalk wrote:
> There are still some 84pin chips out there(Altera & Xilinx). Sometimes
> they are pulls, or some 5V tolerant xilinx xc95l
I still have a few 84 pin PLCC XC95108 5V CPLDs Originally, I did a
tape controller design with one before Xilinx
On 2023-09-22 12:04, Mike Katz via cctalk wrote:
I'm working on the design for an Omnibus (PDP-8/E) debug board and I am
not very good at circuit design. I know there are programs that will
compile something that looks like C into Verilog/VHDL/Abel/Etc for use
on some kind of large (more than
> On Sep 22, 2023, at 12:04 PM, Mike Katz via cctalk
> wrote:
>
> I'm working on the design for an Omnibus (PDP-8/E) debug board and I am not
> very good at circuit design. I know there are programs that will compile
> something that looks like C into Verilog/VHDL/Abel/Etc for use on some
FPGA's tend to be ALL 3.3 volts or less today. Cmos 22v10's are nice
chips to program that is still working at 5 volts. FPGA's also have
high learning curve to catch the bugs and gotya's.
I got tl866 ii + programer and it works great under windows, with wincupl.
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