Congrats Michael!
This is the first time in 24 years that an OS has been run on this
system.
Ed# and crew at smecc.org
In a message dated 8/2/2015 7:20:02 A.M. US Mountain Standard Time,
michael.99.thomp...@gmail.com writes:
With a lot of help from Dave Gesswein and Warren
great news. hope for further success.
On Sun, Aug 2, 2015 at 10:19 AM, Michael Thompson
michael.99.thomp...@gmail.com wrote:
With a lot of help from Dave Gesswein and Warren Stearns we were able to
get the MARK12 PDP-12 tape formatting program off a LINCtape and int paper
tape format. Running
With a lot of help from Dave Gesswein and Warren Stearns we were able to
get the MARK12 PDP-12 tape formatting program off a LINCtape and int paper
tape format. Running it showed that a diode on the field-0 core stack had
failed during the week making memory in the range of 4000-5000 unusable.
Some progress on the PDP-12. We borrowed a TU56 tape head from the TU56 in
the warehouse and replaced the broken right head. We reran ran
MAINDEC-12-D3AE-PB PDP-12 TAPE CONTROL TEST, PART 1 OF 2. The diag runs OK,
so at least the timing track in the borrowed tape head is OK.
We reran
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Jay Jaeger
Sent: 16 July 2015 01:56
To: cctalk@classiccmp.org
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
Saul is indeed cited in the ACM article,
http
On 07/16/2015 01:12 AM, Dave G4UGM wrote:
Apparently the School of Medicine, Manchester University, England
were given a 7090 which they later connected to a PDP-8. A bit of
googling turned this up :-
http://www.ukuug.org/newsletter/linux-newsletter/linux@uk12/dclark.shtml
Nice article.
This brings up a good point: just because a D Flip Flop is clocked by
something other than a system-wide (or subsystem-wide) clock does not
turn it into a latch. Flip flops can clocked by combinatorial inputs.
This can be a problematic thing of course, as they can cause glitch
problems - had a
Saul is indeed cited in the ACM article,
http://dl.acm.org/citation.cfm?id=365671
I know that Purdue had some folks that did their own maintenance, and
sure, by the late 1960's one could certain pick them up cheap - the gold
scrappers were not quite the issue they became later. I know this
The 8086 had four segment registers:
. . .
That certainly sounds reasonable, but,
have you noticed the difference in behavior of 8086/8088 V 80386?
Haven't. The SDM covers Pentium forward (and even then it attempts to
document the differences between the different models). I think
Lots of machines supported variable length operands (like the machine
you reference in the link, IBM S/360, Burroughs, etc. etc. However,
machines with variable length instructions not split into any kind of
word boundary are not as common.
This isn't about whether a machine was good or bad /
From: Sean Caron
Many examples of blinkenlights eye candy throughout computer history
It wasn't _just_ eye candy; it was a real help in problem debugging (when the
machine was stopped), and you could tell a lot about what the machine was
doing (when it was running) from the way the
I remember when U Wisconsin ECE got their PDP-11/20 and I saw DOS
FORTRAN get stuck for the very first time. I told the more senior
student who was responsible for getting things going, preparing
documentation, etc. that the machine was in a loop, and never coming
out. He laughed at me, claiming
On Jul 15, 2015, at 2:14 PM, Chuck Guzis ccl...@sydex.com wrote:
On 07/15/2015 10:48 AM, Jay Jaeger wrote:
Lots of machines supported variable length operands (like the machine
you reference in the link, IBM S/360, Burroughs, etc. etc. However,
machines with variable length instructions
1440s and 1460s were architecturally 1401s (much as the 7010 is
architecturally a 1410 - software compatible). I have not heard of a
1450 anywhere, but seem to recall hearing about at least one 1460 and
see photos of them online.
On 7/15/2015 12:26 AM, William Donzelli wrote:
In the 7000
On 7/14/2015 7:36 PM, Jon Elson wrote:
On the system 360 CPUs, they did not use flip-flops like we are used
to, today. They used latches ... Since these were discrete transistor
implementations, a real flip-flop was too expensive, but a latch could
be implemented in about
Sigh. Again, the difference is between how OPERANDS were formatted vs.
INSTRUCTIONS. As I said, I agree that lots of machines had variable
length operands (including a couple at the bit level, which the 1400
series did not do except for an individual character). But darn few had
variable length
That would certainly be closer than any of the other examples that have
been thrown in the discussion. But it, of course, is much newer than
the 1400 series. IIRC, the discussion started when someone suggested
that there were quite a few machines that were similar to the 1400
series in terms of
On 7/15/15 10:28 AM, Noel Chiappa wrote:
Speaking of lights for feedback, anyone remember the 'run bar' - or whatever
they called it, my memory fails me - on the display on the Lisp Machines?
Actually, it was a series, IIRC - one for the CPU, one for the disk, etc. The
machine didn't have
On 07/15/2015 01:49 PM, Jay Jaeger wrote:
That would certainly be closer than any of the other examples that have
been thrown in the discussion. But it, of course, is much newer than
the 1400 series. IIRC, the discussion started when someone suggested
that there were quite a few machines that
On 07/15/2015 01:30 PM, ben wrote:
Quick look on the web ... ARG! Max segment length 64K something.
Well, even in the late 70s, 64KB was still a goodly chunk of memory in
the microprocessor world. Which reminds me...
To bore you with another STAR tale--the machine had two page sizes--the
On 7/15/2015 3:54 PM, Chuck Guzis wrote:
On 07/15/2015 01:30 PM, ben wrote:
Quick look on the web ... ARG! Max segment length 64K something.
Well, even in the late 70s, 64KB was still a goodly chunk of memory in
the microprocessor world. Which reminds me...
To bore you with another STAR
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Paul
Koning
Sent: 13 July 2015 17:03
To: General Discussion: On-Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
On Jul 13, 2015, at 8:35 AM, Jay
From: Rich Alderson
Changing from PDP-8 operation to LINC operation was a matter of a
physical switch.
Err, not according to the Small Computer Handbook (1967 Edition), which
covers the LINC-8 in detail - at least, as I understand it? See, for instance,
pg. 307 A LINC HALT
Seconded; I was just leafing through A DEC view of hardware systems
design again last week and I had noticed that footnote and was wondering
myself ... the PDP-3 must be the rarest of them all :O I wonder if there
are any surviving leftovers?
Best,
Sean
On Tue, Jul 14, 2015 at 1:04 AM, Paul
On Jul 13, 2015, at 8:52 PM, Johnny Billquist b...@update.uu.se wrote:
On 2015-07-13 21:16, Rich Alderson wrote:
...
[2] With memory management, 18 or 22, in 16-bit segments. Late models could
use separate instruction and data segments, for a total of 128KB in use
at
one
Discussion: On-Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
On Jul 13, 2015, at 8:35 AM, Jay Jaeger cu...@charter.net wrote:
Another alternative would be to build a machine up from a Field
Programmable Gate Array (e.g., the Digilent Nexys2 FPGA
On 7/13/2015 10:02 AM, Paul Koning wrote:
A different approach is to reproduce the actual logic design. FPGAs
can be fed gate level models, though that’s not the most common
practice as I understand it. But if you have access to that level
of original design data, the result can be quite
On 7/14/2015 9:46 AM, Jay Jaeger wrote:
My work has been using structural models, at the gate level, in VHDL
(Verilog would be fine, too, of course). Individual components (for
example, a piece of an IBM SMS card, or in my existing case, gates made
available to student engineers that were
On Jul 14, 2015, at 11:46 AM, Jay Jaeger cu...@charter.net wrote:
...
Using the structural / gate level techniques, one does run into some
issues, most of which have (or will probably have) solutions:
1) R/S latches composed of gates in a combinatorial loop. The problems
this causes
Date: Mon, 13 Jul 2015 01:52:09 -0400
From: Kip Koon computer...@sc.rr.com
Subject: RE: PDP-12 at the RICM
Hi Michael,
I would be most interested in finding out more about this effort. Do you
have ongoing pictures documenting this effort? I'd love to have a PDP 8,
11, 12 someday, but I
Date: Sun, 12 Jul 2015 16:10:10 -0500
From: Jay Jaeger cu...@charter.net
Subject: Re: PDP-12 at the RICM
BTW, if there are particular cards you need / are bad, in addition to
the actual PDP-12, I have the backplanes and cards for a 2nd one, so if
you need something, we could probably work
On 7/13/2015 4:59 PM, Michael Thompson wrote:
Date: Mon, 13 Jul 2015 01:52:09 -0400
From: Kip Koon computer...@sc.rr.com
Subject: RE: PDP-12 at the RICM
Hi Michael,
I would be most interested in finding out more about this effort. Do you
have ongoing pictures documenting this effort? I'd
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ANDY HOLT
Sent: 14 July 2015 10:20
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
- Original
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old architecture, when
pretty much the same result
On 07/14/2015 11:14 AM, Alan Hightower wrote:
Determinism. Unless you run your software simulator bare-metal - which
most aren't - cycle accuracy is always a race. Before you say modern
processors are 100,000 times faster than emulated ones - so just spin
wait until the next virtual time tick,
On Jul 14, 2015, at 3:27 PM, tony duell a...@p850ug1.demon.co.uk wrote:
That sounds like a bug in the original. If you have a set of flops clocked
by some signal, and it matters that the
outputs don’t all change at the same time, then the original wasn’t reliable
either.
It is
That sounds like a bug in the original. If you have a set of flops clocked
by some signal, and it matters that the
outputs don’t all change at the same time, then the original wasn’t reliable
either.
It is very poor design, and not something that I would do, but it certainly was
done in
On 7/14/2015 11:27 AM, Paul Koning wrote:
On Jul 14, 2015, at 11:46 AM, Jay Jaeger cu...@charter.net wrote:
...
Using the structural / gate level techniques, one does run into some
issues, most of which have (or will probably have) solutions:
1) R/S latches composed of gates in a
On 2015-07-14 19:52, Noel Chiappa wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at update.uu.se
wrote:
??? What segments??? The PDP-11 have a plain simple page table. No
segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of their machines.
--
Will
On 07/14/2015 04:49 PM, Jay Jaeger wrote:
Not necessarily. For example, it is impossible to find an IBM 1410, as
far as I know. But there ARE 1415 consoles I knew of a while back, and
there are certainly 729s and 1403 printers and 1402 card read/punch
units up and running.
There are plenty
On 7/14/2015 11:16 AM, ben wrote:
Here is the link you have been waiting for, IBM 1130 in FPGA and in the
FLESH.
http://ibm1130.blogspot.ca/
Ben.
Thanks for that link. It looks very interesting after a quick glance. I
am sure that I will run into many of the same issues with the SMS
On 2015-07-14 16:09, Paul Koning wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist b...@update.uu.se wrote:
On 2015-07-13 21:16, Rich Alderson wrote:
...
[2] With memory management, 18 or 22, in 16-bit segments. Late models could
use separate instruction and data segments, for a
On Jul 14, 2015, at 4:41 PM, Chuck Guzis ccl...@sydex.com wrote:
On 07/14/2015 10:29 AM, Paul Koning wrote:
The accuracy of the FPGA depends on the approach. If it’s a
structural (gate level) model, it is as accurate as the schematics
you’re working from. And as I mentioned, that
The 12-bit computer that I translated originally had *independent* 1
micro-second clocks in each of four racks. The processor derived a 3
micro-second clock from that, but also a second clock that was out of
phase with the CPU master clock, used to sync. signals coming in from
the other racks
On 7/14/2015 7:36 PM, Jon Elson wrote:
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of
On Tue, Jul 14, 2015 at 3:28 PM, tony duell a...@p850ug1.demon.co.uk wrote:
If you mean 6 different clock sources (i.e. clocks delayed from each other,
etc) then that
is not typical of a 1970s minicomputer in my experience.
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
From: Johnny Billquist
While the pages are variable in length, each page starts at an 8K
virtual address boundary.
Which is another difference between PDP-11 'pages', and real pages as used on
every other machine of the period which had virtual memory: normally, page
sizes were
On 7/14/2015 7:31 PM, Chuck Guzis wrote:
Seymour Cray should have used kinetic sculptures on his machines as part
of eye candy, I guess. Or maybe more chrome...
You got a nice love seat. I could see a early cray style maching in a FPGA
but what good is number crunching if you don't have the
On 07/14/2015 06:55 PM, Jay Jaeger wrote:
Architecturally, it was pretty much the last of its kind: the last of
the BCD decimal arithmetic machines, which also makes it interesting.
It has also become much more obscure than the 1401, which it followed,
because not nearly as many were made and
I think a lot of things drive the popularity of the PDP-8 from nostalgia to
historicity to perhaps the relative simplicity of the CPU to understand as
a design example in computer architecture ... IMO the machine is just a bit
too limited to be much fun to program in assembly ... although maybe
In the 7000 series, the 1410 equivalent was the 7010 - architecturally
compatible, ran the same software, but implemented in 7000 series
technology. It came along in 1962. So that was really the last one to
be introduced of its ilk.
Other than clones and the like (e.g., from folks like
That's an interesting argument against using FPGAs in this sort of
application; definitely food for thought. That said, from my (admittedly
limited hobbyist and academic exposure) to FPGAs, I would expect the bulk
of of whatever's being implemented would be fairly device-agnostic ...
certainly you
As well, some early microprocessors used multiple clocks i.e. the TMS9900.
Best,
Sean
On Tue, Jul 14, 2015 at 8:04 PM, Eric Smith space...@gmail.com wrote:
On Tue, Jul 14, 2015 at 3:28 PM, tony duell a...@p850ug1.demon.co.uk
wrote:
If you mean 6 different clock sources (i.e. clocks
Johnny Billquist wrote:
On 2015-07-14 19:52, Noel Chiappa wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at
update.uu.se wrote:
??? What segments??? The PDP-11 have a plain simple page
table. No
segments anywhere in sight. And each page is 8K.
I know the
On 7/14/15 9:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
My experience of FPGAs is that if you design a circuit for an FPGA it will
work. If you take an existing design
feed it into a schematic capture program and compile it for an FPGA then it
won't.
Actually, you can, and I have done so - provided that the original
machine was slow
The 8086 had four segment registers:
CS - Code segment, used with IP register
DS - Data segment
SS - Stack segment, used with SP and BP registers
ES - Extra segment, used with DI for string instructions as
destination (DS:SI
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination (DS:SI as source)
You could override
On 7/14/15 9:53 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
On 7/14/2015 10:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
Sometimes it is fun to be a relative expert on an obscure branch of
knowledge that few people are even aware of.
I worked on one when I was a student, as an operator, programmer and
systems programmer. Tweaked its FORTRAN compiler to spit out text error
messages instead of just error codes. The
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of their machines.
On the system 360 CPUs,
Meh. You take your machines and I'll take mine. :) The IBM 1410 is a
machine I know well, so I know how it is supposed to work, and I have
detailed information in the form of the ALD's and the CE training
materials to go with it, plus software including diagnostics and
operational software I can
Yes, the S/360 had packed decimal - but much more limited in length, and
no wordmark concept.
The 7070 and 7080 were contemporary with the 1410, not after it. They
did not follow it. While data representations were somewhat similar,
the instruction formats were very different.
he 7080 (which
On 07/14/2015 09:16 PM, Jay Jaeger wrote:
Other than clones and the like (e.g., from folks like Honeywell), I'm
not aware of any other machines with a similar architecture to the 1401
and 1410. Name them?
Well, how about a bit-addressable, variable field length machine that
had not only
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Chuck
Guzis
Sent: 14 July 2015 18:17
To: gene...@classiccmp.org; discuss...@classiccmp.org:On-Topic and Off-
Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at update.uu.se wrote:
??? What segments??? The PDP-11 have a plain simple page table. No
segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them 'pages', but I can't think of any
other machine
On 07/14/2015 10:35 AM, ben wrote:
I've run the Cyber emulator as well as various SIMH emulators from time
to time, but it's just not the same as the real thing--it's not even
remotely the same.
You can still the old computer blinking lights movie props.
On a Cyber? What blinking lights?
On 7/14/2015 11:17 AM, Chuck Guzis wrote:
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old
On 7/13/15 9:54 PM, Paul Anderson wrote:
Hi Rich,
Which one was possibility built for NSA? I missed the [1] footnote. Do you
know more about the story?
this is the source for the wikipedia entry on the PDP-3
http://www.decconnection.org/announcements.htm
February 14,
Message-
From: cctech [mailto:cctech-boun...@classiccmp.org] On Behalf Of Michael
Thompson
Sent: Sunday, July 12, 2015 7:32 PM
To: cctech
Subject: Re: PDP-12 at the RICM
The RICM Learning Lab was nice and cool today so we spent the afternoon chasing the
LGP GP=GPC PRESET in the TC12 LINCtape
From: Rich Alderson
PDP-1212-bit word, PDP-8/i + LINC hybrid
Err, DEC sold a PDP-8/LINC hybrid themselves (interesting machine, it's
covered in one of the standard PDP-8 processor manuals), before the PDP-12
came out; the -12 was basically a re-engineered version of the 8/LINC.
On 13 July 2015 at 16:09, Noel Chiappa j...@mercury.lcs.mit.edu wrote:
From: Rich Alderson
PDP-1212-bit word, PDP-8/i + LINC hybrid
Err, DEC sold a PDP-8/LINC hybrid themselves (interesting machine, it's
covered in one of the standard PDP-8 processor manuals), before the PDP-12
From: Noel Chiappa
Sent: Monday, July 13, 2015 1:10 PM
From: Rich Alderson
PDP-12 12-bit word, PDP-8/i + LINC hybrid
Err, DEC sold a PDP-8/LINC hybrid themselves (interesting machine, it's
covered in one of the standard PDP-8 processor manuals), before the PDP-12
came out; the -12
/wiki/index.php/Kip_Koon
-Original Message-
From: cctech [mailto:cctech-boun...@classiccmp.org] On Behalf Of Michael
Thompson
Sent: Sunday, July 12, 2015 7:32 PM
To: cctech
Subject: Re: PDP-12 at the RICM
The RICM Learning Lab was nice and cool today so we spent the afternoon
J. Victor Nahigian donated some M221 and M222 boards for the processor and
TC12 LINCtape controller. They are in pretty bad condition, but are
repairable. Warren wrote a test program for the M222 boards, and some of
the just donated boards actually work OK. It will be nice to have some
spares.
The RICM Learning Lab was nice and cool today so we spent the afternoon
chasing the LGP GP=GPC PRESET in the TC12 LINCtape controller. With a
logic analyzer connected to lots of the TC12 signals were were able to
chase down the signal that is causing the fault. We are now not sure if the
signal
Two transistors on the front panel that turn on PC and MA lights failed.
They were painful to replace. Hopefully this won't be a weekly ritual.
We ran more of the LINC mode processor diagnostics. All that we could
figure out with no documentation worked OK. Hopefully someone has the
missing
We are missing the documentation for many of the MAINDEC-12 diagnostics.
MAINDEC-12-D0AB-PB PDP-12 CP TEST 2
MAINDEC-12-D0BA-PB INSTRUCTION TEST PART 1
MAINDEC-12-D0CB-PB PDP-12 CP TEST 3
MAINDEC-12-D0SA-PB Auto Priority Interrupt
MAINDEC-12-D1AC-PB Extended Memory Control
MAINDEC-12-D1BA-PB JMP
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