Re: early (pre-1971) edge-triggered D flip-flop ICs
On 7/21/2017 8:12 AM, Vincent Slyngstad via cctalk wrote: From: Ethan Dicks: Thursday, July 20, 2017 11:08 AM On Thu, Jul 20, 2017 at 11:35 AM, Norman Jaffe via cctech wrote: Or, in today's dollars - $58. Ouch. Wow! That's many dollars per flip and or flop! If that lasted any time at all, one can see the rationale behind things like DEC's Posibus/Negibus (in which fantastic amounts of cabling that costs $$$ today are expended to save a gate or two). Vince But remember you paid for the small size of the part. I expect you could pack the parts fairly dense on a PCB. Ben.
Re: early (pre-1971) edge-triggered D flip-flop ICs
> On Jul 21, 2017, at 10:12 AM, Vincent Slyngstad via cctalk > wrote: > > From: Ethan Dicks: Thursday, July 20, 2017 11:08 AM >> On Thu, Jul 20, 2017 at 11:35 AM, Norman Jaffe via cctech >> wrote: >>> Or, in today's dollars - $58. Ouch. >> Wow! That's many dollars per flip and or flop! > > If that lasted any time at all, one can see the rationale behind things like > DEC's Posibus/Negibus (in which fantastic amounts of cabling that costs $$$ > today are expended to save a gate or two). The economies of different parts of a design clearly change over the years. Now you can add thousands of transistors at zero cost, it's just a microscopic added amount of space on a large chip. But when each transistor was a separate component that had to be built, packaged, purchased, and soldered into place, things were a bit different. Bob Supnik described it well with his "economy of gates" note a few months ago. Wires vs. circuitry is one obvious example. We use high speed serial buses now because logic is cheap. In decades past, lots of wires were used because wires and connectors were cheaper than transistors -- and also because the space taken up by those wires wasn't the predominant issue compared to the space taken up by logic. I remember being amazed when DEC's SDI disk interconnect came out (in the RA80). I didn't understand then what was going on: the transition from "save logic, add wires" to "we can afford to use logic to cut it down to just a few wires". paul
Re: early (pre-1971) edge-triggered D flip-flop ICs
From: Ethan Dicks: Thursday, July 20, 2017 11:08 AM On Thu, Jul 20, 2017 at 11:35 AM, Norman Jaffe via cctech wrote: Or, in today's dollars - $58. Ouch. Wow! That's many dollars per flip and or flop! If that lasted any time at all, one can see the rationale behind things like DEC's Posibus/Negibus (in which fantastic amounts of cabling that costs $$$ today are expended to save a gate or two). Vince
Re: early (pre-1971) edge-triggered D flip-flop ICs
" In final use, the parts had power applied for no more then an hour." ...and then something goes boom??? Marc On Thu, Jul 20, 2017 at 9:19 AM, Pete Lancashire via cctalk < cctalk@classiccmp.org> wrote: > In 1978 the place I worked the cost per SSI/MSI TTL 38510 device was > between $100 and $200 each by the time they were released to production. > the key is the 38510 and the testing. In final use, the parts had power > applied for no more then an hour. > > -pete > > On Thu, Jul 20, 2017 at 1:35 AM, Eric Smith via cctalk < > cctalk@classiccmp.org> wrote: > > > On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks > > wrote: > > > > > I have no datasheet, but I have examples on DEC M-series FLIP-CHIP > > > modules from my PDP-8/L, c. 1968. > > > > > > I am pretty sure I have examples with 1968 date codes and possibly > > > 1967 date codes. > > > > > > > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and > > SN7474N (plastic DIP), priced at $8.00. > > > > >
Re: early (pre-1971) edge-triggered D flip-flop ICs
That's a lot cheaper than the first logic ICs I remember, the Fairchild µL series RTL logic ICs. Two 2-input NOR gates, or a single JK flop, or 4? inverters per package. 10-wire transistor cans. paul > On Jul 20, 2017, at 11:35 AM, Norman Jaffe via cctech > wrote: > > Or, in today's dollars - $58. Ouch. > > From: "General Discussion" > To: "cctalk" > Sent: Thursday, July 20, 2017 1:35:47 AM > Subject: Re: early (pre-1971) edge-triggered D flip-flop ICs > > On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks wrote: > >> I have no datasheet, but I have examples on DEC M-series FLIP-CHIP >> modules from my PDP-8/L, c. 1968. >> >> I am pretty sure I have examples with 1968 date codes and possibly >> 1967 date codes. >> > > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and > SN7474N (plastic DIP), priced at $8.00.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On Thu, Jul 20, 2017 at 11:35 AM, Norman Jaffe via cctech wrote: > Or, in today's dollars - $58. Ouch. Wow! That's many dollars per flip and or flop! > On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks wrote: >> I have no datasheet, but I have examples on DEC M-series FLIP-CHIP >> modules from my PDP-8/L, c. 1968. >> >> I am pretty sure I have examples with 1968 date codes and possibly >> 1967 date codes. > > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and > SN7474N (plastic DIP), priced at $8.00.
Re: early (pre-1971) edge-triggered D flip-flop ICs
In 1978 the place I worked the cost per SSI/MSI TTL 38510 device was between $100 and $200 each by the time they were released to production. the key is the 38510 and the testing. In final use, the parts had power applied for no more then an hour. -pete On Thu, Jul 20, 2017 at 1:35 AM, Eric Smith via cctalk < cctalk@classiccmp.org> wrote: > On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks > wrote: > > > I have no datasheet, but I have examples on DEC M-series FLIP-CHIP > > modules from my PDP-8/L, c. 1968. > > > > I am pretty sure I have examples with 1968 date codes and possibly > > 1967 date codes. > > > > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and > SN7474N (plastic DIP), priced at $8.00. > >
Re: early (pre-1971) edge-triggered D flip-flop ICs
Or, in today's dollars - $58. Ouch. From: "General Discussion" To: "cctalk" Sent: Thursday, July 20, 2017 1:35:47 AM Subject: Re: early (pre-1971) edge-triggered D flip-flop ICs On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks wrote: > I have no datasheet, but I have examples on DEC M-series FLIP-CHIP > modules from my PDP-8/L, c. 1968. > > I am pretty sure I have examples with 1968 date codes and possibly > 1967 date codes. > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and SN7474N (plastic DIP), priced at $8.00.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On Wed, Jul 19, 2017 at 11:29 PM, Ethan Dicks wrote: > I have no datasheet, but I have examples on DEC M-series FLIP-CHIP > modules from my PDP-8/L, c. 1968. > > I am pretty sure I have examples with 1968 date codes and possibly > 1967 date codes. > Thanks! Also, the 1967 Allied catalog lists the SN7474 (flat pack) and SN7474N (plastic DIP), priced at $8.00.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On Wed, Jul 19, 2017 at 6:10 PM, Eric Smith via cctalk wrote: > I'm interested in the history of the logic design for the edge-triggered D > flip-flop, as used in the SN7474... > > Does anyone know what year the SN7474 was introduced, or have an early > datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st > Edition? I have no datasheet, but I have examples on DEC M-series FLIP-CHIP modules from my PDP-8/L, c. 1968. I am pretty sure I have examples with 1968 date codes and possibly 1967 date codes. I do find that when repairing DEC equipment of this vintage, the two most common parts to fail are the 7474s and the 7440s. Others have also written up their repair experiences and these two parts top the list for common failures. -ethan
Re: early (pre-1971) edge-triggered D flip-flop ICs
Thanks for all the info, Brent! The MECL II MC1022 is an edge-triggered D flip-flop using master-slave design. I'll have to look up the others you mentioned, especially the National DM8510 and Sprague NE8828. I've previously overlooked the MC778 mW RTL D flip-flop, which also uses a variant of the three-SR design. However, it is a cruder device than the MC3060 and SN7474, in that its asynchronous preset and clear only work when the clock input is high, whereas they work at any time in the MC3060 and SN7474. I haven't analyzed the circuit, but I'm guessing that they simply didn't gate the preset and clear inputs into the master flip-flop of the MC778, but only into the slave FF. Best regards, Eric
Re: early (pre-1971) edge-triggered D flip-flop ICs
On 7/19/17 5:36 PM, Brent Hilpert via cctalk wrote: > I also have the 65 TI catalog, which introduces the 5400 / future-7400 > series, but the family is only half-a-dozen packages of gates and the 5470 FF > at that point. > I started scanning Allied Electronics catalogs since they give prices and show product lines for early ICs I'll do a few more, but I lost interest once I came across http://www.alliedcatalogs.com/ Don't like the Javascript mung wrapped around it though.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On 2017-Jul-19, at 5:01 PM, Al Kossow via cctalk wrote: > On 7/19/17 4:40 PM, Brent Hilpert via cctalk wrote: > >> There are near-type cross-refs in the 69 book to the National DM8510, >> Sprague NE8828, Sprague USN7474, and Signetics N7474. >> >> I can take and email you photos of the applicable pages if you like. >> Don't have a web site up right now to put them up on. >> > > They should all be on bitsavers. If not, i'll scan the backlog for stragglers > > Eric's interest in the guts of the D flip-flop has been around for a while and > I've been watching for early references. You don't seem to have the '69 catalog up, but you do already have the '67-68, which appears to include the same info about the 7474 as the '69 I was looking at. I also have the 65 TI catalog, which introduces the 5400 / future-7400 series, but the family is only half-a-dozen packages of gates and the 5470 FF at that point.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On 7/19/17 4:40 PM, Brent Hilpert via cctalk wrote: > There are near-type cross-refs in the 69 book to the National DM8510, Sprague > NE8828, Sprague USN7474, and Signetics N7474. > > I can take and email you photos of the applicable pages if you like. > Don't have a web site up right now to put them up on. > They should all be on bitsavers. If not, i'll scan the backlog for stragglers Eric's interest in the guts of the D flip-flop has been around for a while and I've been watching for early references.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On 2017-Jul-19, at 3:10 PM, Eric Smith via cctalk wrote: > I'm interested in the history of the logic design for the edge-triggered D > flip-flop, as used in the SN7474. The design is composed of three set-reset > latches (six NAND gates total) per flip-flop. > > Does anyone know what year the SN7474 was introduced, or have an early > datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st > Edition? > > The earliest datasheet I've found using this specific logic design for an > edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola > MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The > MC3060 is covered in the Motorola 1968 IC databook, on page 4-138. > > I've searched US patents for edge-triggered flip-flop design, but have not > found one specifically for the three S-R latch design. > > The subject came up as a result of a discussion on a private mailing list > regarding the fact that the conventional J-K master-slave flip-flop design > is NOT edge-triggered; pulses on J and/or K while the clock is high but > stable can affect the Q (and not-Q) outputs of the FF at the following > falling edge of the clock. That behavior is known as "pulse catching", and > such a flip-flop is properly called pulse-triggered or level-triggered, but > not edge-triggered. Early datasheets on J-K master-slave flip-flops > actually had correct terminology and specifically stated that J and K > should not change while the clock is high. The 1969 TI TTL IC Catalog presents slightly more info about the 7474, compared to the minimal table-oriented presentation of the 73 databook. Extract; Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. After the clock input threshold voltage has been passed, the data input (D) is locked out. These dual flip-flops have the same clocking characteristics of the SN5470/SN7470 gated (edge-triggerred) flip-flop circuits, . . . A transistor level schematic is present as well. The internal operation of the 7474 is discussed in the Sams book "TTL" by George Flynn / 1974. A decent page+ of text , but I haven't read it in depth so don't really know how good an explanation it is. Cursorily, it seems to be just a logic explanation that anyone could figure out by working through the logic diagram, not an electrical level explanation. There are near-type cross-refs in the 69 book to the National DM8510, Sprague NE8828, Sprague USN7474, and Signetics N7474. I can take and email you photos of the applicable pages if you like. Don't have a web site up right now to put them up on.
Re: early (pre-1971) edge-triggered D flip-flop ICs
On 07/19/2017 03:10 PM, Eric Smith via cctalk wrote: > I'm interested in the history of the logic design for the edge-triggered D > flip-flop, as used in the SN7474. The design is composed of three set-reset > latches (six NAND gates total) per flip-flop. > > Does anyone know what year the SN7474 was introduced, or have an early > datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st > Edition? > > The earliest datasheet I've found using this specific logic design for an > edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola > MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The > MC3060 is covered in the Motorola 1968 IC databook, on page 4-138. It's interesting. I pulled out my Moto 1969 databook, and while the 7400 series numbers jump for 7473 to 7475, but MC7479 is listed as an exact replacement for the TI 7474. There are, of course, earlier edge-triggered flip-flops in other logic families; e.g., the MC1022 ECL flop. --Chuck
