[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. Thanks, I'll take another look. Rereading my previous comment I just wanted to clarify one part so it's not misunderstood. I said " I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience. I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4612099 , @craig.topper wrote: > In D152279#4612087 , @MaskRay wrote: > >> I am still interested in moving this forward. What should be done here? If >> the decision is to keep

[PATCH] D157663: [Driver] Default riscv*- triples to -fdebug-default-version=4

asb accepted this revision. asb added a comment. LGTM, this seems like a good workaround. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157663/new/ https://reviews.llvm.org/D157663 ___ cfe-commits

[PATCH] D157497: feat: Migrate isArch16Bit

asb added a comment. Is there some separate discussion thread or proposal about this refactoring and its motivations? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157497/new/ https://reviews.llvm.org/D157497

[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

asb accepted this revision. asb added a comment. I just wanted to say thank you for your work on the named arguments tablegen feature. This and D154067 are good showcases of the readability improvement. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D151547: [RISCV] Remove experimental for zihintntl

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM - just see the very minor corrections inline. Thanks! Comment at: clang/test/Preprocessor/riscv-target-features.c:146 // RUN: %clang -target riscv32-unknown-linux-gnu

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

asb added a comment. Putting this behind an attribute for now makes sense given that we don't seem to have consensus on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 let alone how to manage any migration. I'm slightly wary of merging this with a generic attribute (currently

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan: I think this is good to go if you rebase now D156221 landed and add a release note. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

This revision was automatically updated to reflect the committed changes. Closed by commit rGe3c57fdd8439: [clang][RISCV] Fix bug in ABI handling of empty structs with hard FP calling… (authored by asb). Changed prior to commit: https://reviews.llvm.org/D142327?vs=546012=547684#toc

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 546012. asb added a comment. This update includes test coverage for the bug that was fixed in the reverted version of the patch. Thanks @rogfer01 for the smaller test case. To my surprise, cvise stripped out almost everything and test_s9 in abi-empty-structs.c

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 544349. asb added a comment. I've updated the patch to fix the reported issue (adding an additional check to detectFPCCEligibleStruct). What I haven't been able to do so far is to extract a test case that shows the issue indicated by @SixWeining without relying

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

asb added a comment. This seems functionally correct to me, but I'd welcome opinions from others who work more with the C intrinsics on if this is the best way to implement the overloading. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. imkiva wrote: > wangpc wrote: > > I think the comment is outdated

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. In D151547#4531062 , @jacquesguan wrote: > https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, > any more advice about this patch? Just that it needs a release note, and we need the newly defined overloaded

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb reopened this revision. asb added a comment. This revision is now accepted and ready to land. Reopening as I've reverted following Roger's bug report. Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:178 return false; -if (isEmptyRecord(getContext(), Ty, true)) +

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG17a58b3ca7ec: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling… (authored by asb). Herald added a subscriber: wangpc. Changed

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan yes I agree, let's hold off on merging this until that PR is merged as it looks like it's quite close. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. I remain concerned about exposing the intrinsics if they're not yet agreed as finalised. I see there is now a PR to add them to riscv-c-api doc https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 I'd be OK with merging this now if the intrinsics were temporarily

[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Should add a release note as well, but otherwise LGTM. My understanding is that all of the intrinsics this exposes have the same level of stability / finalisation as the other vector intrinsics,

[PATCH] D155339: Enable zba and zbs for RISCV64 Android

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155339/new/ https://reviews.llvm.org/D155339 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

asb added a reviewer: eopXD. asb added a comment. Adding eop as a reviewer. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 ___ cfe-commits mailing list

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG29f630a1ddcb: [RISCV][MC] MC layer support for the experimental zacas extension (authored by asb). Changed prior to commit:

[PATCH] D154683: [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154683/new/ https://reviews.llvm.org/D154683 ___

[PATCH] D154681: [RISCV] Split __builtin_riscv_xperm4/8 into separate _32 and _64 builtins.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154681/new/ https://reviews.llvm.org/D154681 ___

[PATCH] D154577: [RISCV] Use 'long' in sha512 builtin tests. NFC

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154577/new/ https://reviews.llvm.org/D154577 ___

[PATCH] D154567: [RISCV] Use ClangBuiltin in IntrinsicsRISCV.td to map some scalar crypto builtins to IR intrinsic.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154567/new/ https://reviews.llvm.org/D154567 ___

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 535372. asb edited the summary of this revision. asb added a comment. Herald added a subscriber: wangpc. Update to 1.0-rc1 (no code changes needed). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files:

[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Agreed that looking at https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are no changes that need to be reflected on the LLVM side beyond the version bump here. LGTM

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6101d720cb49: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings (authored by asb). Changed prior to commit:

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb added a comment. Herald added a subscriber: wangpc. All feedback so far has been positive and this has two LGTMs, but I also recognise this patch has been left for a while. Heads up that I intend to commit this towards the end of the working day Monday UK time unless anyone has any

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

asb added a comment. OK, if this patch is going to verify the table is sorted then SupportedExtensions and SupportedExperimentalExtensions probably deserve a comment to explicitly note they must be kept in sort order. Otherwise, still LGTM. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153170/new/ https://reviews.llvm.org/D153170 ___

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 531244. asb added a comment. Rebase and ping. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4415974 , @MaskRay wrote: > However, RISC-V `-msmall-data-limit=` is probably a case warranting a > difference. > The global pointer relaxation has a very limited value (benchmarked by > multiple parties, including a

[PATCH] D152627: [RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. llvm/test/Bitcode is the other place the autoupgrade tests could go, but it looks like it's not used any more frequently for such tests than llvm/test/CodeGen/$tgt/. Repository: rG LLVM

[PATCH] D152628: [RISCV] Add __builtin_riscv_zip/unzip for Zbkb to match gcc.

asb added a comment. I'm not super familiar with these builtins so this might be a silly question why are the new builtins added in this patch LiLi (long int) rather than ZiZi (int32_t) like the old `_32` suffixed builtins? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D152627: [RISCV] Change the immediate argument to Zvk intrinsics/builtins to i8.

asb added a comment. The patch title should indicate "from i8 to i32" or similar? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152627/new/ https://reviews.llvm.org/D152627 ___ cfe-commits mailing list

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. One of the key things we've been discussing on this at the LLVM call is that we probably want to keep the small data limit for embedded targets. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152279/new/

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4403940 , @phosek wrote: > We're planning to default to `-msmall-data-limit=0` for Android and Fuchsia > so I'm supportive of this change because it means less complexity and fewer > differences between platforms. > > I

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan I'm not sure on the standardisation process or status for these intrinsics. Perhaps @kito-cheng has an idea? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

asb added a comment. Could you please post a separate patch that has a test that will show the codegen change (and demonstrate how it is unchanged when zbb or xtheadbb)? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151867/new/

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating the mistake we made with the V extension where we exposed intrinsics that weren't yet finalised. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

asb added inline comments. Comment at: clang/include/clang/Basic/AttrDocs.td:2347 -Only ``*m1_t`` (LMUL=1) types are supported at this time. +For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the LMULo +of the type before passing to the attribute.

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa1455de74d95: [RISCV][MC] Add support for experimental Zvfbfwma extension (authored by asb). Changed prior to commit:

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

This revision was automatically updated to reflect the committed changes. Closed by commit rGb18a81966499: [RISCV][MC] Add support for experimental Zvfbfmin extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

This revision was automatically updated to reflect the committed changes. Closed by commit rG35ff5eba1646: [RISCV][MC] Add support for experimental Zfbfmin extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147610/new/

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8e8237686346: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled (authored by asb). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

asb created this revision. asb added reviewers: craig.topper, kito-cheng, realqhc. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 523026. asb added a comment. Rebase and ping (also checked there have been no relevant spec changes since this patch was posted). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files:

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 523018. asb edited the summary of this revision. asb added a comment. Now updated to version 0.6 of the spec (was previously blocked on a new PDF being tagged and uploaded). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 523017. asb edited the summary of this revision. asb added a comment. Now updated to version 0.6 of the specification (was previously blocked on a new PDF being tagged). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 523016. asb edited the summary of this revision. asb added a comment. Now updated to reflect v0.6 of the spec and should be ready for final review and merge https://github.com/riscv/riscv-bfloat16/releases/tag/main CHANGES SINCE LAST ACTION

[PATCH] D128612: RISC-V big-endian support implementation

asb added a comment. In D128612#4349259 , @djtodoro wrote: > In D128612#4345912 , @asb wrote: > >> In D128612#4337037 , @djtodoro >> wrote: >> >>> Hi! I am wondering if

[PATCH] D128612: RISC-V big-endian support implementation

asb added a comment. Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it would be helpful from a review perspective to write down at least a simple plain-text description of the changes to the psABI doc needed to reflect the BE ABI implemented by GCC (and soon LLVM),

[PATCH] D145071: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled

This revision was automatically updated to reflect the committed changes. Closed by commit rG560065b6ecd5: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled (authored by asb). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit:

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. Just noting for posterity that we discussed this at last week's RISC-V sync-up call and I think the tentative conclusion (there weren't particularly strong views) was that experiments CSRs should really be gated by -menable-experimental-extensions, with the CSR names gated

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

asb added a comment. In D149314#4302312 , @reames wrote: > In D149314#4302300 , @aaron.ballman > wrote: > >> In D149314#4302266 , @asb wrote: >> >>> In D149314#4302203

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

asb added a comment. In D149314#4302203 , @aaron.ballman wrote: > Is this a potentially breaking change that we need to call out for users to > be aware of? We should mention this in the Clang release notes I think. Repository: rG LLVM Github

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. FWIW, I've reviewed the CSR numbers vs the spec so LGTM from that perspective. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148066/new/ https://reviews.llvm.org/D148066 ___

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. In D148066#4294924 , @kito-cheng wrote: >> My concern would be that as we don't gate CSR names on enabling the relevant >> extension, people could start using CSR names and encodings that could >> change, without opting in via

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

asb added a comment. I just wanted to check on whether this is ready to review? Also, to what degree are these intrinsics standardised and where is the relevant specification for them? Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D148094: [DRAFT][clang][CodeGen] Break up TargetInfo.cpp [6/6]

asb added a comment. +1 on this refactoring being a good idea. The RISC-V changes seem fine to me (haven't done a detailed line by line review). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148094/new/ https://reviews.llvm.org/D148094

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb created this revision. asb added reviewers: reames, craig.topper, kito-cheng. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb updated this revision to Diff 517106. asb added a comment. Add missing doc comment update. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149246/new/ https://reviews.llvm.org/D149246 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-arch.c

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb updated this revision to Diff 517105. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149246/new/ https://reviews.llvm.org/D149246 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-arch.c llvm/lib/Support/RISCVISAInfo.cpp llvm/unittests/Support/RISCVISAInfoTest.cpp

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb created this revision. asb added reviewers: reames, kito-cheng, craig.topper, jrtc27, joshua-arch1. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148962/new/ https://reviews.llvm.org/D148962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. I'd appreciate some riscv32 RUN lines for completeness, but otherwise LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148817/new/

[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

asb added a comment. In D148483#4283898 , @ego wrote: > Thanks for the clarification. I went with the additional alignment. I used to > overdo vertical alignment but it was beaten out of me by the Google C++ style > guide and automatic formatters.

[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGcb7dffdc9a83: [RISCV] Zvk (vector crypto) specification update to 0.5.1… (authored by ego, committed by asb). Herald added a project: clang. Herald

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

asb added a comment. I'm starting to think we should just remove the ordering rules for z/s/x altogether when parsing arch strings I see that gcc 12.2.0 actually requires s and then z: [asb@purge ~]$ riscv64-linux-gnu-gcc -march=rv64imafdc_svinval_zicbom t.c -c [asb@purge ~]$

[PATCH] D148634: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2a5661c84158: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description (authored by asb). Herald added a project: clang. Herald added a

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

asb added a comment. @joshua-arch1: I've posted D146815 to fix the canonical ordering and directly committed rGa35e67fc5be654a7efdfa6125343b90f8960a487 to add some test coverage.

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D147935: [RISCV] Add SiFive extension support

asb accepted this revision. asb added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147935/new/ https://reviews.llvm.org/D147935 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

asb added a comment. In D148034#4262991 , @MaskRay wrote: > In D148034#4260376 , @asb wrote: > >> Will `--[no-]relax-gp` make its way into a minor gcc point release or do we >> need to wait for the next major

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. In D148066#4262379 , @reames wrote: > I would be fine landing this as experimental before ratification. I see no > real downside to doing that My concern would be that as we don't gate CSR names on enabling the relevant

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 512745. asb added a comment. Rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm.org/D147612 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 512744. asb added a comment. Rebase. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org/D147611 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 512743. asb edited the summary of this revision. asb added a comment. Rebase and use the new encoding suggested in https://github.com/riscv/riscv-bfloat16/issues/33 - hoping for the commits that alter the encoding to be pushed to the spec repo and a new PDF

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. This extension doesn't appear to be ratified but you've listed it in the table of ratified extensions and treated it as a ratified extension in RISCVISAInfo.cpp. I know that given we don't do checking for CSR names the distinction feels a bit academic, but I don't think

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

asb added a comment. Will `--[no-]relax-gp` make its way into a minor gcc point release or do we need to wait for the next major release? In terms of this breaking GNU users - isn't it the case that without this option, they may get silently broken code when using the shadow call stack?

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

asb added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:51 // CHECK-NOT: __riscv_zcf {{.*$}} +// CHECK-NOT: __riscv_zcmp // CHECK-NOT: __riscv_h {{.*$}} jrtc27 wrote: > Does this really belong in an MC patch? We typically do

[PATCH] D147935: [RISCV] Add SiFive extension support

asb added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:465 RVV_REQ_FullMultiply = 1 << 1, + RVV_REQ_xsfvcp = 1 << 2, Nit: It would better match the surrounding capitalisation to call this RVV_REQ_Xsfvcp Repository:

[PATCH] D147978: [RISCV] Remove getCPUFeaturesExceptStdExt.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147978/new/ https://reviews.llvm.org/D147978 ___

[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147986/new/ https://reviews.llvm.org/D147986 ___

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb accepted this revision. asb added a comment. In D146463#4255927 , @paulkirth wrote: > @asb Are we happy with the state of consensus w.r.t. using `x3`? I think the > lingering concerns from the psABI discussion have been resolved. Yes, all LGTM

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb added a comment. Ok, looks like the consensus I thought we had isn't quite there on the psABI thread - Andrew Waterman has some concerns. We should let that discussion play out some more. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb added a comment. In D146463#4247050 , @paulkirth wrote: > @asb, @craig.topper, @jrtc27 Are there any remaining considerations for us > here? From the discussions in psABI and sig-toolchain, I think we have a > consensus that this is the approach

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 511082. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm.org/D147612 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 511081. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org/D147611 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 511080. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147610/new/ https://reviews.llvm.org/D147610 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. I also understand that Rocket and SCR-1 support zicsr and zifencei in all standard configurations (and their respective repos seem to confirm this). Repository: rG LLVM Github Monorepo

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks (though see minor note about tweaking commit message to clarify the change). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147179/new/

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

asb added a comment. I've added a couple of inline comments, but otherwise this seems fine to me. I'd suggest updating the patch description to reference Philip's documentation patch (which was posted soon after this), and also to explain why there are no codegen changes (I think "Either

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd3291c692c0a: [RISCV][MC] Add support for the experimental zicond extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE

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