https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/92997
>From 7c1e44455a343cef3c5ab0da22c9971888cf Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 22 May 2024 02:37:04 -0400
Subject: [PATCH 1/3] [PowerPC] Support -fpatchable-function-entry
For now
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC64
+
+define void @f0() {
+; CHECK-LABEL: f0:
+; CHECK-NOT:
@@ -6,15 +6,20 @@
// RUN: %clang -target loongarch64 %s -fpatchable-function-entry=1,0 -c -###
2>&1 | FileCheck %s
// RUN: %clang -target riscv32 %s -fpatchable-function-entry=1,0 -c -### 2>&1
| FileCheck %s
// RUN: %clang -target riscv64 %s -fpatchable-function-entry=1,0 -c
@@ -0,0 +1,4 @@
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -fsyntax-only -verify %s
+
+// expected-error@+1 {{'patchable_function_entry' attribute is not yet
supported on AIX}}
+__attribute__((patchable_function_entry(0))) void f();
chenzheng1030 wrote:
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/92997
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@@ -6681,7 +6681,9 @@ void Clang::ConstructJob(Compilation , const JobAction
,
StringRef S0 = A->getValue(), S = S0;
unsigned Size, Offset = 0;
if (!Triple.isAArch64() && !Triple.isLoongArch() && !Triple.isRISCV() &&
-!Triple.isX86())
+
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s
--check-prefixes=CHECK,PPC32
chenzheng1030 wrote:
Thank you, changed the triple. Little endian is not going to be supported in
this patch.
https://github.com/chenzheng1030 commented:
> So PPC64 can use ELFv2 for Triple::OpenBSD. We probably want to diagnose this
> OS for PPC64, since with ELFv2 we might emit separate local and global entry
> points which means only certain values can be passed to
> -fpatchable-function-entry
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/92997
>From 751d80c61f0e42daa3796a8270e186153dd9413f Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 22 May 2024 02:37:04 -0400
Subject: [PATCH 1/3] [PowerPC] Support -fpatchable-function-entry
For now
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/93267
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@@ -3833,6 +3833,11 @@ def note_cannot_use_trivial_abi_reason : Note<
"it is polymorphic|"
"it has a base of a non-trivial class type|it has a virtual base|"
"it has a __weak field|it has a field of a non-trivial class type}1">;
+def warn_ppc_musttail_maybe_ignored:
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/93267
musttail does not often possible to be generated on PPC targets as when calling
to a function defined in another module, PPC needs to restore the TOC pointer.
To restore the TOC pointer, compiler needs to
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/92997
>From 751d80c61f0e42daa3796a8270e186153dd9413f Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 22 May 2024 02:37:04 -0400
Subject: [PATCH 1/2] [PowerPC] Support -fpatchable-function-entry
For now
@@ -0,0 +1,4 @@
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -fsyntax-only -verify %s
+
+// expected-error@+1 {{'patchable_function_entry' attribute is not yet
supported on AIX}}
+__attribute__((patchable_function_entry(0))) void f();
chenzheng1030 wrote:
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/92997
For now only PPC big endian Linux 32 and 64 bit are supported.
PPC little endian Linux has XRAY support for 64-bit.
PPC AIX has different patchable function entry implementations.
Fixes #63220
Fixes
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/90619
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@@ -479,14 +479,6 @@ static void addTocDataOptions(const llvm::opt::ArgList
,
return false;
}();
- // Currently only supported for small code model.
- if (TOCDataGloballyinEffect &&
- (Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("large") ||
-
@@ -6167,16 +6166,12 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDNode *Tmp = CurDAG->getMachineNode(
isPPC64 ? PPC::ADDIStocHA8 : PPC::ADDIStocHA, dl, VT, TOCbase, GA);
-// On AIX if the symbol has the toc-data attribute it will be defined
-// in the
https://github.com/chenzheng1030 approved this pull request.
LGTM just some nits. I don't think it needs another review for them from my
side.
Please commit when @diggerlin is also happy.
Thanks very much for adding this support.
https://github.com/llvm/llvm-project/pull/90619
@@ -1292,8 +1291,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
unsigned Op = MI->getOpcode();
-// Change the opcode to load address for tocdata
-TmpInst.setOpcode(Op == PPC::ADDItocL8 ? PPC::ADDI8 : PPC::LA);
+// Change the opcode to
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@@ -1,16 +1,13 @@
// RUN: %clang -### --target=powerpc-ibm-aix-xcoff -mcmodel=medium -mtocdata
%s 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-NOTOC %s
+// RUN: | FileCheck -check-prefix=CHECK-TOC %s
chenzheng1030 wrote:
nit: since all the check prefix
https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/90467
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@@ -111,6 +111,20 @@ vector __bool long long v_bll4; // expected-error
{{use of 'long long' with
#endif
__vector long double vv_ld3;// expected-error {{cannot use 'long
double' with '__vector'}}
vector long double v_ld4; // expected-error {{cannot
@@ -1191,6 +1191,10 @@ void DeclSpec::Finish(Sema , const PrintingPolicy
) {
// Validate and finalize AltiVec vector declspec.
if (TypeAltiVecVector) {
+// Complex vector types are not supported.
+if (TypeSpecComplex != TSC_unspecified)
+ S.Diag(TSCLoc,
https://github.com/chenzheng1030 commented:
Thanks very much for taking care of PPC.
https://github.com/llvm/llvm-project/pull/90467
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https://github.com/chenzheng1030 approved this pull request.
LGTM with one nit. Thanks for adding this support.
https://github.com/llvm/llvm-project/pull/88829
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@@ -6,6 +6,9 @@
// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S
-emit-llvm \
// RUN:%s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
+// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-dynamic-tls -S
-emit-llvm \
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Author: Chen Zheng
Date: 2024-04-19T08:52:28-04:00
New Revision: aa39b0b13e3b56ac072acff2660dbef9db45bca0
URL:
https://github.com/llvm/llvm-project/commit/aa39b0b13e3b56ac072acff2660dbef9db45bca0
DIFF:
https://github.com/llvm/llvm-project/commit/aa39b0b13e3b56ac072acff2660dbef9db45bca0.diff
Author: Chen Zheng
Date: 2024-04-19T03:39:17-04:00
New Revision: b2323f43e3cdb52b4e15a7d4f434cd5c64740dd4
URL:
https://github.com/llvm/llvm-project/commit/b2323f43e3cdb52b4e15a7d4f434cd5c64740dd4
DIFF:
https://github.com/llvm/llvm-project/commit/b2323f43e3cdb52b4e15a7d4f434cd5c64740dd4.diff
https://github.com/chenzheng1030 approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/85040
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@@ -72,4 +72,74 @@ define i64 @rldimi_intrinsic(i64 %a) {
ret i64 %r3
}
+define i64 @rldimi5(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi5:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 4, 3, 8, 40
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64
@@ -10764,30 +10764,53 @@ SDValue
PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getRegister(PPC::R2, MVT::i32);
case Intrinsic::ppc_rldimi: {
+assert(Subtarget.isPPC64() && "rldimi is only available in 64-bit!");
+if
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https://github.com/chenzheng1030 commented:
Looks almost good to me though I have a comment for the all one mask case.
https://github.com/llvm/llvm-project/pull/85040
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@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res =
@@ -5093,9 +5094,33 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
, unsigned BuiltinID,
case PPC::BI__builtin_ppc_rlwnm:
return SemaValueIsRunOfOnes(TheCall, 2);
case PPC::BI__builtin_ppc_rlwimi:
- case PPC::BI__builtin_ppc_rldimi:
return
@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res =
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+;
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+;
chenzheng1030 wrote:
The failure in the buildkite should be unrelated. But would be better to double
confirm.
https://github.com/llvm/llvm-project/pull/82968
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@@ -1,70 +1,117 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8
+; NOTE: Assertions have been autogenerated by
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+;
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+;
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/82968
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https://github.com/chenzheng1030 approved this pull request.
LGTM except two comments in the case change. One is a nit and the other one
should be other issue unrelated to this patch.
Thanks for implementing this.
https://github.com/llvm/llvm-project/pull/82968
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+;
chenzheng1030 wrote:
> If you run into issues using normal integer ops, please file bugs. Most
> people aren't going to hand-tune their code like this; builtins like this are
> at best an ugly workaround.
Yes, a user should not try to write source code(using compiler builtins) to
just emit
@@ -641,6 +641,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine
,
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ // setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
@@ -10722,6 +10723,20 @@ static bool getVectorCompareInfo(SDValue Intrin, int
,
return true;
}
+bool isContiguousMask(const APInt , unsigned , unsigned ,
chenzheng1030 wrote:
Is it possible to reuse `isRunOfOnes()`/`isRunOfOnes64()` in
https://github.com/chenzheng1030 closed
https://github.com/llvm/llvm-project/pull/79109
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chenzheng1030 wrote:
> I don't have any further comments, so I think LGTM.
Thanks Amy.
https://github.com/llvm/llvm-project/pull/79109
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chenzheng1030 wrote:
Patch updated.
https://github.com/llvm/llvm-project/pull/79109
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https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/79109
>From 014b10f43e2d3f8564940e21033cee77c3c0c10e Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Tue, 23 Jan 2024 03:25:01 -0500
Subject: [PATCH 1/2] [PowerPC] Diagnose invalid combination with
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/79109
Moved from https://reviews.llvm.org/D126302
The current behaviour with these three options is quite undesirable:
-mno-altivec -mvsx allows VSX to override no Altivec, thereby turning on both
-msoft-float
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG ) const {
+ SDLoc Dl(Op);
+ MachineFunction =
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG ) const {
+ SDLoc Dl(Op);
+ MachineFunction =
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG ) const {
+ SDLoc Dl(Op);
+ MachineFunction =
@@ -77,4 +77,196 @@ return: ; preds = %entry
ret i32 %retval3
}
-declare i32 @llvm.get.rounding() nounwind
+define void @setrnd_tozero() {
+; PPC32-LABEL: setrnd_tozero:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb0 30
+; PPC32-NEXT:mtfsb1
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG ) const {
+ SDLoc Dl(Op);
+ MachineFunction =
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@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG ) const {
+ SDLoc Dl(Op);
+ MachineFunction =
https://github.com/chenzheng1030 commented:
Maybe we can do some perf test between this expansion for set rounding mode and
the system library's version for `fesetround()`. On AIX, I saw some
improvements were introduced in the system library's implementation.
https://github.com/chenzheng1030 approved this pull request.
LGTM with nits.
https://github.com/llvm/llvm-project/pull/76495
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@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128,
"V1LLLiULLiULLi", "", "vsx")
// Set the floating point rounding mode
BUILTIN(__builtin_setrnd, "di", "")
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")
chenzheng1030
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@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128,
"V1LLLiULLiULLi", "", "vsx")
// Set the floating point rounding mode
BUILTIN(__builtin_setrnd, "di", "")
+// Barrier for instruction motion
chenzheng1030 wrote:
Can we add some comments here
@@ -40,6 +40,12 @@ EnablePEVectorSpills("ppc-enable-pe-vector-spills",
cl::desc("Enable spills in prologue to vector
registers."),
cl::init(false), cl::Hidden);
+static cl::opt
+
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@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec --ppc-enable-load-store-multiple < %s \
+; RUN: | FileCheck %s
+
+; CHECK: # %bb.0:# %entry
+; CHECK-NEXT:
@@ -2399,6 +2405,29 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
return AllSpilledToReg;
}
+static void findContinuousLoadStore(ArrayRef CSI,
+Register ) {
+ unsigned I = 1, E = CSI.size(), BeginI = 0;
+ for (; I < E; ++I) {
+
@@ -3412,13 +3416,23 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
https://github.com/chenzheng1030 approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/71814
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@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if
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@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if
https://github.com/chenzheng1030 approved this pull request.
@ecnelises Let's first fix this for AIX. Could you please help to create a
github issue for the SPE? Thanks.
https://github.com/llvm/llvm-project/pull/70652
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@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation , const
JobAction ,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && CM ==
@@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///<
-fno-hip-fp32-correctly-rounde
CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is
enabled.
CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get
unique
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/70255
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https://github.com/chenzheng1030 approved this pull request.
Thanks for adding this. LGTM
https://github.com/llvm/llvm-project/pull/70255
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@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation , const
JobAction ,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && CM ==
@@ -5723,7 +5723,7 @@ void Clang::ConstructJob(Compilation , const JobAction
,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && (CM ==
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool FullRegisterNames = false;
chenzheng1030 wrote:
Using a target feature bit for
@@ -833,6 +833,22 @@ TargetInfo::CreateTargetInfo(DiagnosticsEngine ,
if (!Target->handleTargetFeatures(Opts->Features, Diags))
return nullptr;
+ // If TuneCPU is set, check if it contains all instruction sets needed by
+ // current feature map.
+ if
https://github.com/chenzheng1030 closed
https://github.com/llvm/llvm-project/pull/68476
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@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
Done.
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/3] [AIX] recognize vsr in inline asm for AIX
---
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
FP and VMX
@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return
https://github.com/chenzheng1030 approved this pull request.
Make sense to me. Thanks.
https://github.com/llvm/llvm-project/pull/68681
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https://github.com/chenzheng1030 edited
https://github.com/llvm/llvm-project/pull/68476
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@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
This is what
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - |
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs
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