[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,426 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,426 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,426 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

https://github.com/bogner commented: Ran into some problems when building `clang-docs-html` to look at this, so here are some notes on fixing those issues. I'll do another pass on the content next. https://github.com/llvm/llvm-project/pull/83933 ___

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,426 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

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[clang] [HLSL] enforce unsigned types for reversebits (PR #86720)

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[clang] [HLSL] enforce unsigned types for reversebits (PR #86720)

@@ -54,31 +29,6 @@ uint16_t4 test_bitreverse_ushort4(uint16_t4 p0) } #endif -// CHECK: define noundef i32 @ -// CHECK: call i32 @llvm.bitreverse.i32( -int test_bitreverse_int(int p0) -{ - return reversebits(p0); -} bogner wrote: Alright, let's get this

[clang] [HLSL] enforce unsigned types for reversebits (PR #86720)

@@ -54,31 +29,6 @@ uint16_t4 test_bitreverse_ushort4(uint16_t4 p0) } #endif -// CHECK: define noundef i32 @ -// CHECK: call i32 @llvm.bitreverse.i32( -int test_bitreverse_int(int p0) -{ - return reversebits(p0); -} bogner wrote: In that case we might

[clang] [HLSL] enforce unsigned types for reversebits (PR #86720)

@@ -54,31 +29,6 @@ uint16_t4 test_bitreverse_ushort4(uint16_t4 p0) } #endif -// CHECK: define noundef i32 @ -// CHECK: call i32 @llvm.bitreverse.i32( -int test_bitreverse_int(int p0) -{ - return reversebits(p0); -} bogner wrote: Will these implicitly

[clang] [HLSL] Add validation for the -enable-16bit-types option (PR #85340)

@@ -0,0 +1,20 @@ +// RUN: not %clang_dxc -enable-16bit-types -T cs_6_0 -HV 2016 %s 2>&1 | FileCheck -check-prefix=both_invalid %s +// RUN: not %clang_dxc -enable-16bit-types -T lib_6_4 -HV 2017 %s 2>&1 | FileCheck -check-prefix=HV_invalid %s +// RUN: not %clang_dxc

[clang] [HLSL] Add validation for the -enable-16bit-types option (PR #85340)

@@ -753,7 +753,10 @@ def err_drv_hlsl_unsupported_target : Error< "HLSL code generation is unsupported for target '%0'">; def err_drv_hlsl_bad_shader_required_in_target : Error< "%select{shader model|Vulkan environment|shader stage}0 is required as

[clang] [HLSL] Fix for build break introduced by #85662 (PR #85839)

bogner wrote: I've gone ahead and merged this since it fixes the build break. In the future when you see a build break, please just revert the breaking change to get the build green again and then work on the fixed patch. It's unfair to others using trunk to have to wait on a fix for an

[clang] [HLSL] Fix for build break introduced by #85662 (PR #85839)

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[clang] [HLSL] Fix for build break introduced by #85662 (PR #85839)

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[clang] [llvm] [HLSL] implement `clamp` intrinsic (PR #85424)

@@ -132,12 +134,60 @@ static bool expandRcpIntrinsic(CallInst *Orig) { return true; } +static Intrinsic::ID getCorrectMaxIntrinsic(Type *elemTy, +Intrinsic::ID clampIntrinsic) { bogner wrote: I could see us

[clang] [llvm] [HLSL] implement `clamp` intrinsic (PR #85424)

@@ -252,6 +252,116 @@ double3 ceil(double3); _HLSL_BUILTIN_ALIAS(__builtin_elementwise_ceil) double4 ceil(double4); +//===--===// +// clamp builtins

[clang] [llvm] [HLSL] implement `clamp` intrinsic (PR #85424)

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[clang] [llvm] [HLSL] implement `clamp` intrinsic (PR #85424)

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[clang] [llvm] [HLSL] implement the `isinf` intrinsic (PR #84927)

@@ -18050,6 +18050,21 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, /*ReturnType=*/Op0->getType(), Intrinsic::dx_frac, ArrayRef{Op0}, nullptr, "dx.frac"); } + case Builtin::BI__builtin_hlsl_elementwise_isinf: { +Value *Op0 =

[clang] [llvm] [HLSL] implement the `isinf` intrinsic (PR #84927)

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[clang] [llvm] [HLSL] implement the `isinf` intrinsic (PR #84927)

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[clang] [llvm] [HLSL] Implement `rsqrt` intrinsic (PR #84820)

@@ -0,0 +1,26 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for rsqrt are generated for float and half. +; CHECK:call float @dx.op.unary.f32(i32 25, float %{{.*}}) +; CHECK:call half @dx.op.unary.f16(i32 25, half %{{.*}})

[clang] [llvm] [HLSL] Implement `rsqrt` intrinsic (PR #84820)

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[clang] [llvm] [HLSL] Implement `rsqrt` intrinsic (PR #84820)

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[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,105 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + +; CHECK:icmp ne i1 %{{.*}}, false bogner wrote: Folks usually put a space between `CHECK:` and the

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

https://github.com/bogner approved this pull request. A couple more very minor notes on the tests, then this LGTM https://github.com/llvm/llvm-project/pull/84526 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,105 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + +; CHECK:icmp ne i1 %{{.*}}, false +define noundef i1 @any_bool(i1 noundef %p0) { bogner wrote: Probably

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

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[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,187 @@ +//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL encoding--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,133 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + + +target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64" +target triple =

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,133 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + + +target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64" +target triple =

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,133 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + + +target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64" +target triple =

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,187 @@ +//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL encoding--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,133 @@ +; RUN: opt -S -dxil-op-lower < %s | FileCheck %s + +; Make sure dxil operation function calls for any are generated for float and half. + + +target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64" +target triple =

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,187 @@ +//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL encoding--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,187 @@ +//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL encoding--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -0,0 +1,187 @@ +//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL encoding--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -5254,7 +5250,11 @@ bool CheckAllArgsHaveFloatRepresentation(Sema *S, CallExpr *TheCall) { QualType ExpectedType = S->Context.FloatTy; for (unsigned i = 0; i < TheCall->getNumArgs(); ++i) { QualType PassedType = TheCall->getArg(i)->getType(); -if

[clang] [llvm] [DXIL] `exp`, `any`, `lerp`, & `rcp` Intrinsic Lowering (PR #84526)

@@ -18015,38 +18015,11 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Value *X = EmitScalarExpr(E->getArg(0)); Value *Y = EmitScalarExpr(E->getArg(1)); Value *S = EmitScalarExpr(E->getArg(2)); -llvm::Type *Xty = X->getType(); -

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,258 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,258 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [Doc][HLSL] Add documentation for root signature. (PR #83933)

@@ -0,0 +1,258 @@ + +HLSL Root Signatures + + +.. contents:: + :local: + +Usage += + +In HLSL, the `root signature +`_ +defines what types of resources are

[clang] [HLSL][docs] Document hlsl.h in the HLSL docs (PR #84081)

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[clang] [llvm] [HLSL] implement exp intrinsic (PR #83832)

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[clang] [llvm] [HLSL] implement `mad` intrinsic (PR #83826)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/83826 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Add -HV option translation to clang-dxc.exe (PR #83938)

@@ -8545,6 +8545,10 @@ def dxc_entrypoint : Option<["--", "/", "-"], "E", KIND_JOINED_OR_SEPARATE>, Group, Visibility<[DXCOption]>, HelpText<"Entry point name">; +def dxc_hlsl_version : Option<["--", "/", "-"],

[clang] [HLSL] Add -HV option translation to clang-dxc.exe (PR #83938)

@@ -0,0 +1,13 @@ +// RUN: %clang_dxc -T lib_6_4 -HV 2016 %s 2>&1 -### | FileCheck -check-prefix=2016 %s +// RUN: %clang_dxc -T lib_6_4 -HV 2017 %s 2>&1 -### | FileCheck -check-prefix=2017 %s +// RUN: %clang_dxc -T lib_6_4 -HV 2018 %s 2>&1 -### | FileCheck

[clang] [llvm] [HLSL] implement `mad` intrinsic (PR #83826)

@@ -19812,11 +19821,13 @@ bool Sema::SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall) { Args[I] = Converted.get(); } - int ArgOrdinal = 1; - for (Expr *Arg : Args) { -if (checkFPMathBuiltinElementType(*this, Arg->getBeginLoc(), Arg->getType(), -

[clang] [llvm] [HLSL][SPIR-V] Add SV_DispatchThreadID semantic support (PR #82536)

@@ -342,8 +343,19 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<> , return B.CreateCall(FunctionCallee(DxGroupIndex)); } if (D.hasAttr()) { -llvm::Function *DxThreadID = CGM.getIntrinsic(Intrinsic::dx_thread_id); -return buildVectorInput(B,

[clang] [llvm] [HLSL] implement the rcp intrinsic (PR #83857)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/83857 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement the rcp intrinsic (PR #83857)

@@ -0,0 +1,27 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm -disable-llvm-passes -verify -verify-ignore-unexpected bogner wrote: While it's certainly worth exploring the options here I

[clang] [llvm] [HLSL] implement `mad` intrinsic (PR #83826)

@@ -19800,7 +19808,8 @@ bool Sema::SemaBuiltinVectorMath(CallExpr *TheCall, QualType ) { return false; } -bool Sema::SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall) { +bool Sema::SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall, +

[clang] [llvm] [HLSL] implement `mad` intrinsic (PR #83826)

@@ -5298,6 +5298,14 @@ bool Sema::CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_mad: { +if (checkArgCount(*this, TheCall, 3)) + return true; +if

[clang] [llvm] [HLSL] implement `mad` intrinsic (PR #83826)

@@ -19812,11 +19821,13 @@ bool Sema::SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall) { Args[I] = Converted.get(); } - int ArgOrdinal = 1; - for (Expr *Arg : Args) { -if (checkFPMathBuiltinElementType(*this, Arg->getBeginLoc(), Arg->getType(), -

[clang] [llvm] [HLSL][SPIR-V] Add SV_DispatchThreadID semantic support (PR #82536)

@@ -342,8 +343,19 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<> , return B.CreateCall(FunctionCallee(DxGroupIndex)); } if (D.hasAttr()) { -llvm::Function *DxThreadID = CGM.getIntrinsic(Intrinsic::dx_thread_id); -return buildVectorInput(B,

[clang] [llvm] [HLSL][SPIR-V] Add SV_DispatchThreadID semantic support (PR #82536)

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[clang] [llvm] [HLSL][SPIR-V] Add SV_DispatchThreadID semantic support (PR #82536)

https://github.com/bogner approved this pull request. LGTM. I don't like how we're choosing an intrinsic but changing that can come in as a follow up if you like. https://github.com/llvm/llvm-project/pull/82536 ___ cfe-commits mailing list

[clang] [HLSL] standardize builtin unit tests (PR #83340)

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[clang] [HLSL] standardize builtin unit tests (PR #83340)

bogner wrote: If we want to talk about guidelines for clang-formatting tests in general we should probably bring it up with the wider LLVM community on discourse. The de facto standard today is that tests should be well formatted like anything else unless there's a good reason not to, but

[clang] [llvm] [HLSL] implementation of lerp intrinsic (PR #83077)

@@ -10266,6 +10266,11 @@ def err_block_on_vm : Error< def err_sizeless_nonlocal : Error< "non-local variable with sizeless type %0">; +def err_vec_builtin_non_vector_all : Error< + "all arguments to %0 must be vectors">; +def err_vec_builtin_incompatible_vector_all : Error<

[clang] [llvm] [HLSL] implementation of lerp intrinsic (PR #83077)

@@ -5169,49 +5169,63 @@ bool Sema::CheckPPCMMAType(QualType Type, SourceLocation TypeLoc) { bool CheckVectorElementCallArgs(Sema *S, CallExpr *TheCall) { assert(TheCall->getNumArgs() > 1); ExprResult A = TheCall->getArg(0); - ExprResult B = TheCall->getArg(1); +

[clang] [llvm] [HLSL] implementation of lerp intrinsic (PR #83077)

https://github.com/bogner approved this pull request. LGTM, but see my comments in #83315 about test case formatting. https://github.com/llvm/llvm-project/pull/83077 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [HLSL] implementation of lerp intrinsic (PR #83077)

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[clang] [llvm] [HLSL] Implementation of the frac intrinsic (PR #83315)

@@ -0,0 +1,69 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \ +// RUN: --check-prefixes=CHECK,NATIVE_HALF +// RUN: %clang_cc1

[clang] [llvm] [HLSL] Implementation of the frac intrinsic (PR #83315)

https://github.com/bogner approved this pull request. LGTM other than the formatting in the test cases https://github.com/llvm/llvm-project/pull/83315 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [HLSL] Implementation of the frac intrinsic (PR #83315)

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[clang] [HLSL] Fix casting asserts (PR #82827)

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[clang] [HLSL] Fix casting asserts (PR #82827)

@@ -4843,7 +4843,7 @@ Sema::PerformImplicitConversion(Expr *From, QualType ToType, .get(); break; case ICK_Floating_Integral: - if (ToType->isRealFloatingType()) + if (ToType->isRealFloatingType() || ToType->hasFloatingRepresentation())

[clang] [HLSL] Fix casting asserts (PR #82827)

@@ -1,4 +1,8 @@ // RUN: %clang_cc1 -triple dxil-unknown-shadermodel6.6-library -S -fnative-half-type -finclude-default-header -o - -ast-dump %s | FileCheck %s +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library

[clang] [HLSL][Doc] Add doc about expected differences (PR #82395)

@@ -0,0 +1,108 @@ + +Expected Differences vs DXC and FXC +=== + +.. contents:: + :local: + +Introduction + + +HLSL currently has two reference compilers, the `DirectX Shader Compiler (DXC)

[clang] [HLSL][Doc] Add doc about expected differences (PR #82395)

@@ -0,0 +1,108 @@ + +Expected Differences vs DXC and FXC +=== + +.. contents:: + :local: + +Introduction + + +HLSL currently has two reference compilers, the `DirectX Shader Compiler (DXC)

[clang] [HLSL][Doc] Add doc about expected differences (PR #82395)

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[clang] [HLSL][Doc] Add doc about expected differences (PR #82395)

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[clang] [HLSL] add BuiltinsHLSL and set it up as target builtins. (PR #81902)

https://github.com/bogner requested changes to this pull request. Hm, on further thought tying the "HLSL" intrinsics to the DirectX backend as target intrinsics like this is probably going to shoot us in the foot with respect to SPIR-V. I think we need to rethink this, and if we are going with

[clang] [HLSL] add BuiltinsHLSL and set it up as target builtins. (PR #81902)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/81902 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Expose `half` types and intrinsics always (PR #81782)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/81782 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Vector standard conversions (PR #71098)

@@ -113,30 +115,12 @@ float2 HowManyFloats(float V) { // up nicely too. // CHECK-LABEL: AllRighty -// CHECK: [[XTmp:%.*]] = alloca <1 x double>, align 8 -// CHECK: [[YTmp:%.*]] = alloca <1 x double>, align 8 -// CHECK: [[ZTmp:%.*]] = alloca <1 x double>, align 8 - -// CHECK:

[clang] [HLSL] Vector standard conversions (PR #71098)

@@ -4772,6 +4788,76 @@ Sema::PerformImplicitConversion(Expr *From, QualType ToType, llvm_unreachable("Improper second standard conversion"); } + if (SCS.Element != ICK_Identity) { +// If SCS.Element is not ICK_Identity the To and From types must be HLSL +//

[clang] [HLSL] Vector standard conversions (PR #71098)

@@ -6432,7 +6432,7 @@ void InitializationSequence::InitializeFrom(Sema , // For HLSL ext vector types we allow list initialization behavior for C++ // constructor syntax. This is accomplished by converting initialization // arguments an InitListExpr late. - if

[clang] [HLSL] Vector standard conversions (PR #71098)

@@ -4772,6 +4788,76 @@ Sema::PerformImplicitConversion(Expr *From, QualType ToType, llvm_unreachable("Improper second standard conversion"); } + if (SCS.Element != ICK_Identity) { +// If SCS.Element is not ICK_Identity the To and From types must be HLSL +//

[clang] [HLSL] Vector standard conversions (PR #71098)

@@ -123,84 +123,83 @@ CompareDerivedToBaseConversions(Sema , SourceLocation Loc, /// GetConversionRank - Retrieve the implicit conversion rank /// corresponding to the given implicit conversion kind. ImplicitConversionRank clang::GetConversionRank(ImplicitConversionKind Kind)

[clang] [HLSL] Vector standard conversions (PR #71098)

https://github.com/bogner approved this pull request. Looks good barring a few minor comments https://github.com/llvm/llvm-project/pull/71098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [HLSL] Vector standard conversions (PR #71098)

https://github.com/bogner edited https://github.com/llvm/llvm-project/pull/71098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC] Add API documentation and annotations (PR #78635)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/78635 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [libc] [compiler-rt] [clang-tools-extra] [flang] [clang] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

https://github.com/bogner closed https://github.com/llvm/llvm-project/pull/78221 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[libc] [flang] [llvm] [clang] [compiler-rt] [clang-tools-extra] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/78221 >From 8903229f71503c1c4291254c355b1692d9d908a3 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Mon, 15 Jan 2024 18:14:07 -0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[clang] [clang-tools-extra] [llvm] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

@@ -0,0 +1,102 @@ +=== +Architecture and Design of DXIL Support in LLVM +=== + +.. contents:: + :local: + +.. toctree:: + :hidden: + +Introduction + + +LLVM supports reading

[clang] [clang-tools-extra] [llvm] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

@@ -0,0 +1,102 @@ +=== +Architecture and Design of DXIL Support in LLVM +=== + +.. contents:: + :local: + +.. toctree:: + :hidden: + +Introduction + + +LLVM supports reading

[clang] [clang-tools-extra] [llvm] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

@@ -0,0 +1,102 @@ +=== +Architecture and Design of DXIL Support in LLVM +=== + +.. contents:: + :local: + +.. toctree:: + :hidden: + +Introduction + + +LLVM supports reading

[clang] [clang-tools-extra] [llvm] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

@@ -0,0 +1,102 @@ +=== +Architecture and Design of DXIL Support in LLVM +=== + +.. contents:: + :local: + +.. toctree:: + :hidden: + +Introduction + + +LLVM supports reading

[clang] [llvm] [clang-tools-extra] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/78221 >From 8903229f71503c1c4291254c355b1692d9d908a3 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Mon, 15 Jan 2024 18:14:07 -0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm] [clang-tools-extra] [clang] [DirectX][docs] Architecture and design philosophy of DXIL support (PR #78221)

https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/78221 >From 8903229f71503c1c4291254c355b1692d9d908a3 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Mon, 15 Jan 2024 18:14:07 -0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[clang] [clang-tools-extra] [llvm] [openmp] [flang] [DirectX] Move DXIL ResourceKind and ElementType to DXILABI.h. NFC (PR #78225)

https://github.com/bogner closed https://github.com/llvm/llvm-project/pull/78225 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[flang] [clang] [clang-tools-extra] [llvm] [openmp] [DirectX] Move DXIL ResourceKind and ElementType to DXILABI.h. NFC (PR #78225)

https://github.com/bogner edited https://github.com/llvm/llvm-project/pull/78225 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [clang] [llvm] [DirectX] Rename DXILOperationCommon.h to DXILABI.h. NFC (PR #78224)

https://github.com/bogner closed https://github.com/llvm/llvm-project/pull/78224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang-tools-extra] [clang] [DirectX] Rename DXILOperationCommon.h to DXILABI.h. NFC (PR #78224)

https://github.com/bogner updated https://github.com/llvm/llvm-project/pull/78224 >From 698fb909b55b9134b23da7ec1c87c75375f950b4 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Mon, 15 Jan 2024 18:32:54 -0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[clang-tools-extra] [libc] [flang] [clang] [compiler-rt] [libcxx] [llvm] [IR] Disallow ZeroInit for spirv.Image (PR #73887)

bogner wrote: This change causes a number of the spir-v backend tests to crash: > Failed Tests (5): > LLVM :: CodeGen/SPIRV/image-unoptimized.ll > LLVM :: CodeGen/SPIRV/read_image.ll > LLVM :: CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll > LLVM ::

[clang] [HLSL][Docs] Add documentation for HLSL functions (PR #75397)

https://github.com/bogner approved this pull request. https://github.com/llvm/llvm-project/pull/75397 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [clang-tools-extra] [libcxx] [lldb] [clang] [libc] [llvm] [libcxxabi] [lld] [flang] [HLSL][DirectX] Move handling of resource element types into the frontend (PR #75674)

https://github.com/bogner closed https://github.com/llvm/llvm-project/pull/75674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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