[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

michaelmaitland added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2381 + if HasVV then { +defvar suffix = !if(!or(HasVS, !eq(NAME, "vsm4r")), "vv", "v"); +// We don't need suffix in Zvkb extension since it's consider as normal

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

michaelmaitland added a comment. Can you please add a description for this patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138810/new/ https://reviews.llvm.org/D138810 ___ cfe-commits mailing list

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

michaelmaitland accepted this revision. michaelmaitland added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150253/new/ https://reviews.llvm.org/D150253

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland added a comment. In D149495#4373768 , @reames wrote: > Let's go ahead and land this as is, we can rework the stylistic pieces once > the linked patches land. This has landed in

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162 + bool hasVInstructionsF16Mininal() const { +return HasStdExtZvfhmin || HasStdExtZvfh; + } michaelmaitland wrote: > jacquesguan wrote: > > craig.topper wrote: > >

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162 + bool hasVInstructionsF16Mininal() const { +return HasStdExtZvfhmin || HasStdExtZvfh; + } jacquesguan wrote: > craig.topper wrote: > > Doesn't HasStdExtZvfh

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

michaelmaitland added a comment. In D150253#4355730 , @jacquesguan wrote: > @michaelmaitland , I update this revision with my local branch. May you have > a look and see what missed compared with you version? I have left some comments on the clang

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

michaelmaitland added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c:15 + + + Do we need a test that checks calls to `__riscv_vfwcvt_f` and `__riscv_vfncvt_f` using type `vfloat16m1_t` without zvfh nor zvfhmin

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

michaelmaitland added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1856 def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; - def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">; + let RequiredFeatures = ["ZvfhminOrZvfh"]

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

michaelmaitland added inline comments. Comment at: clang/lib/Sema/Sema.cpp:2049 +!TI.hasFeature("experimental-zvfhmin")) + Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh"; if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

michaelmaitland added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1856 def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; - def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">; + let RequiredFeatures = ["ZvfhminOrZvfh"]

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. michaelmaitland wrote: > pcwang-thead wrote: > >

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1a855819a87f: [RISCV] Add support for V extenstion in SiFive7 (authored by michaelmaitland). Changed prior to commit:

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. pcwang-thead wrote: > So, are we going to discard

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland updated this revision to Diff 521024. michaelmaitland marked 2 inline comments as done. michaelmaitland added a comment. Use defvar in subroutines. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:15 +class SiFive7IsWorstCaseMX MxList> { + string LLMUL = LargestLMUL.r; + bit c = !eq(mx, LLMUL); pcwang-thead wrote: > I think I have fixed the issue that `defar`

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

michaelmaitland updated this revision to Diff 520847. michaelmaitland marked an inline comment as done. michaelmaitland added a comment. Remove extra space before VLUpperBound. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf9fa8a599704: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland). Repository: rG LLVM

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

michaelmaitland updated this revision to Diff 519921. michaelmaitland added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149497/new/ https://reviews.llvm.org/D149497 Files: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td Index:

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

michaelmaitland added a comment. This revision needs to be reopened because it was committed with changes that are not relevant to this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149497/new/ https://reviews.llvm.org/D149497

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

michaelmaitland added a comment. I had to revert this commit because it failed tests that did not fail during build through phabricator nor local check-all. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149710/new/

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

This revision was automatically updated to reflect the committed changes. Closed by commit rGb77d6f51ba4e: [RISCV] Add Scheduling information for Zfh to SiFive7 model (authored by michaelmaitland). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

This revision was automatically updated to reflect the committed changes. Closed by commit rGcd02b69e75dd: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland). Changed prior to commit: https://reviews.llvm.org/D149497?vs=518924=519854#toc

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG55e196e7718c: [RISCV] Add sifive-x280 processor with all of its extensions (authored by michaelmaitland). Changed prior to commit:

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

michaelmaitland updated this revision to Diff 518925. michaelmaitland added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149498/new/ https://reviews.llvm.org/D149498 Files: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td Index:

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

michaelmaitland updated this revision to Diff 518924. michaelmaitland marked an inline comment as done. michaelmaitland added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149497/new/ https://reviews.llvm.org/D149497 Files:

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

michaelmaitland updated this revision to Diff 518923. michaelmaitland added a comment. Split adding sifive-x280 and vector model between this patch and https://reviews.llvm.org/D149710 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

michaelmaitland created this revision. michaelmaitland added reviewers: craig.topper, kito-cheng, reames, pcwang-thead. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

michaelmaitland added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:176 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba"

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

michaelmaitland marked an inline comment as done. michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:181 + FeatureStdExtZvfh, + FeatureStdExtZba, +

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

michaelmaitland updated this revision to Diff 518089. michaelmaitland added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Add zfh to `clang/test/Driver/riscv-cpus.c` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extenstion in SiFive7

michaelmaitland updated this revision to Diff 518086. michaelmaitland added a comment. Remove zfh from x280 check in `clang/test/Driver/riscv-cpus.c` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/ https://reviews.llvm.org/D149495

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

michaelmaitland created this revision. michaelmaitland added reviewers: craig.topper, kito-cheng, reames. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D149495: Add sifive-x280 processor and support V extenstion in SiFive7

michaelmaitland created this revision. michaelmaitland added reviewers: craig.topper, kito-cheng, reames, pcwang-thead. Herald added subscribers: luke, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

michaelmaitland accepted this revision. michaelmaitland added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149017/new/ https://reviews.llvm.org/D149017

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:703 class VPseudoUSLoadMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), +

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

michaelmaitland added a comment. In D144914#4159291 , @MaskRay wrote: > Sorry I just saw this but I am not sure this is a good idea. Why can't the > user use `--print-supported-cpus` instead? The additional alias doesn't seem > useful. If you can make

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG003078b62d8d: [Clang][Driver] Add -mcpu=help and -mtune=help to clang (authored by michaelmaitland). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

michaelmaitland added a comment. In D144914#4156567 , @reames wrote: > Code and description appear out of sync. (help != list) Personally, I like > the help naming a lot better. Thanks for catching this. I meant to write `help` instead of `list`.

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

michaelmaitland updated this revision to Diff 500907. michaelmaitland added a comment. Change `list` -> `help`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144914/new/ https://reviews.llvm.org/D144914 Files: clang/docs/CommandGuide/clang.rst

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

michaelmaitland created this revision. michaelmaitland added reviewers: craig.topper, reames. Herald added a project: All. michaelmaitland requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Clang currently uses `-mcpu=?`. The `?` causes