[PATCH] D144999: [Clang][MC][MachO]Only emits compact-unwind format for "canonical" personality symbols. For the rest, use DWARFs.

t.p.northover added a comment. I don't think this handles the no-personality case properly. For example this code leads to a DWARF entry now: void bar(int *) noexcept; void foo() { int arr; bar(); } Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D151337: ARM: default to arm_aapcscc (or VFP) for embedded MachO targets.

t.p.northover added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151337/new/ https://reviews.llvm.org/D151337 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D151337: ARM: default to arm_aapcscc (or VFP) for embedded MachO targets.

t.p.northover created this revision. Herald added subscribers: kristof.beyls, mcrosier. Herald added a project: All. t.p.northover requested review of this revision. Herald added a project: clang. These were always intended to be AAPCS targets and LLVM does treat the usual C calling convention

[PATCH] D139182: AArch64: add CodeGen support for FEAT_XS DSB instructions

t.p.northover updated this revision to Diff 493305. t.p.northover added a comment. Thanks for the warning. Now that's settled down a bit I've updated the patch to the new regime. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139182/new/ https://reviews.llvm.org/D139182 Files:

[PATCH] D139182: AArch64: add CodeGen support for FEAT_XS DSB instructions

t.p.northover created this revision. Herald added subscribers: hiraditya, kristof.beyls, mcrosier. Herald added a project: All. t.p.northover requested review of this revision. Herald added projects: clang, LLVM. The new variants like `dsb ishnxs` map naturally to CRm == {16, 20, 24, 28},

[PATCH] D134640: Unwind-tables: move back to original logic outline for kind.

t.p.northover closed this revision. t.p.northover added a comment. Sorry about that, committed as e62b3a9375d8 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134640/new/

[PATCH] D134640: Unwind-tables: move back to original logic outline for kind.

t.p.northover created this revision. t.p.northover added a reviewer: abrachet. Herald added a subscriber: mcrosier. Herald added a project: All. t.p.northover requested review of this revision. Herald added a subscriber: MaskRay. Herald added a project: clang. There are lots of options

[PATCH] D134351: AArch64: add definitions for recent Apple CPUs

t.p.northover closed this revision. t.p.northover added a comment. Thanks, committed as 677da09d0259 . CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134351/new/ https://reviews.llvm.org/D134351

[PATCH] D134351: AArch64: add definitions for recent Apple CPUs

t.p.northover updated this revision to Diff 461858. t.p.northover added a comment. Accidentally clang-formatted the `ampere1` test. Undo that. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134351/new/ https://reviews.llvm.org/D134351 Files: clang/test/Misc/target-invalid-cpu-note.c

[PATCH] D134351: AArch64: add definitions for recent Apple CPUs

t.p.northover created this revision. t.p.northover added a reviewer: ab. Herald added subscribers: hiraditya, kristof.beyls, mcrosier. Herald added a project: All. t.p.northover requested review of this revision. Herald added projects: clang, LLVM. Herald added a subscriber: cfe-commits. This

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover closed this revision. t.p.northover added a comment. Just noticed it'd already been approved with those suggestions, so pushed the revised version: 4388b56d and 58f9abaed4aa

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover updated this revision to Diff 459004. t.p.northover marked an inline comment as done. t.p.northover added a comment. Switched to `enum class`. > You may want to split the patch, with refactoring as the first, and the > Mach-O specific change as the second one. I've got it split

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover updated this revision to Diff 458444. t.p.northover added a comment. Herald added subscribers: bzcheeseman, sdasgup3, wenzhicui, wrengr, cota, teijeong, rdzhabarov, tatianashp, msifontes, jurahul, Kayjukh, grosul1, Joonsoo, stephenneuendorffer, liufengdb, aartbik, mgester,

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover updated this revision to Diff 458443. Herald added subscribers: abrachet, mstorsjo, emaste. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131153/new/ https://reviews.llvm.org/D131153 Files: clang/include/clang/Driver/ToolChain.h clang/lib/Driver/ToolChain.cpp

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover added a comment. > I don't think this is quite correct though? It'll turn off unwind tables for > AArch64 entirely, whereas we want to keep sync unwind tables. You're right, sorry about that. Hopefully this refactoring with MaskRay's suggestion gets it right.

[PATCH] D131153: AArch64: disable asynchronous unwind by default for MachO.

t.p.northover created this revision. Herald added subscribers: kristof.beyls, mcrosier. Herald added a project: All. t.p.northover requested review of this revision. Herald added a subscriber: MaskRay. Herald added a project: clang. AArch64 MachO has a compact unwind format where most functions'

[PATCH] D119788: [AArch64] Add support for -march=native for Apple M1 CPU

t.p.northover added a comment. Sorry, that was an old xnu version, the newest one is https://opensource.apple.com/source/xnu/xnu-7195.81.3/osfmk/mach/machine.h.auto.html which has | `CPUFAMILY_ARM_CYCLONE`| 0x37a09642 | `apple-a7` | | `CPUFAMILY_ARM_TYPHOON`

[PATCH] D119788: [AArch64] Add support for -march=native for Apple M1 CPU

t.p.northover added a comment. Things have moved on since the ARM and (especially) PPC variants of that function were written. That field (despite the name) is now more of an ABI tag and not going to be updated with each CPU. I think the modern replacement for it is `hw.cpufamily` obtained

[PATCH] D103165: Threading: use independent llvm::thread implementation on Apple platforms to increase stack size

t.p.northover closed this revision. t.p.northover added a comment. Thanks Duncan, committed as 727e1c9be3a5 Comment at: llvm/include/llvm/Support/thread.h:107 + + bool joinable() const noexcept { +

[PATCH] D103165: Threading: use independent llvm::thread implementation on Apple platforms to increase stack size

t.p.northover added a comment. Ping. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103165/new/ https://reviews.llvm.org/D103165 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D103165: Threading: use independent llvm::thread implementation on Apple platforms to increase stack size

t.p.northover added inline comments. Comment at: llvm/include/llvm/Support/thread.h:168 +/// stack size request. +class thread { +public: An alternative here would have been to inherit from `std::thread` but that seemed a bit icky to me. Happy to switch if the

[PATCH] D103165: Threading: use independent llvm::thread implementation on Apple platforms to increase stack size

t.p.northover updated this revision to Diff 348958. t.p.northover added a comment. Herald added subscribers: cfe-commits, usaxena95, kadircet, arphaman, hiraditya. Herald added a project: clang-tools-extra. - Add `llvm::thread` for all potential platforms, allowing stack size to be specified. -

[PATCH] D95228: Add swift_async_context parameter attribute mapping to IR equivalent

t.p.northover closed this revision. t.p.northover marked an inline comment as done. t.p.northover added a comment. Thanks, committed as e94fada045fe with the extra tests. Comment at:

[PATCH] D100591: [Clang][AArch64] Disable rounding of return values for AArch64

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. Thanks for updating it. A little disappointing that we can't support BE first-class, but much more important that it's not broken and it's not actually that common. So I think

[PATCH] D100591: [Clang][AArch64] Disable rounding of return values for AArch64

t.p.northover added a comment. On big-endian targets the rounding up to 64-bits (specified in the AAPCS) is significant; it means that structs get passed in the high bits of `x0` rather than low. E.g. https://godbolt.org/z/6v36oexsW. I think this patch would break that. Repository: rG LLVM

[PATCH] D99079: [ARM][AArch64] Require appropriate features for crypto algorithms

t.p.northover added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/ARM.cpp:641 + }); + if ((ItSHA2 != Features.rend()) || (ItSHA2 != Features.rend())) +Features.push_back("-crypto"); Both of these checks are identical. And could we get

[PATCH] D97510: [AArch64][Docs] Release notes 12.x on outline atomics

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. I think this is fine. Comment at: clang/docs/ReleaseNotes.rst:82 + if compilation target supports LSE. Atomic instructions are used directly in + that case.

[PATCH] D97233: Support `#pragma clang section` directives on MachO targets

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. Thanks. I think it looks good too now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97233/new/ https://reviews.llvm.org/D97233

[PATCH] D97233: Support `#pragma clang section` directives on MachO targets

t.p.northover added inline comments. Comment at: clang/lib/Sema/SemaAttr.cpp:304 + if (llvm::Error E = Context.getTargetInfo().isValidSectionSpecifier(SecName)) +Diag(PragmaLoc, diag::err_pragma_section_invalid_for_target) Shouldn't this block return so

[PATCH] D96825: [AArch64] Adding Polynomial vadd Intrinsics support

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. Looks sensible to me. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96825/new/ https://reviews.llvm.org/D96825 ___

[PATCH] D95655: [AArch64] Adding Neon Sm3 & Sm4 Intrinsics

t.p.northover added inline comments. Comment at: clang/test/CodeGen/aarch64-neon-sm4-sm3.c:5 + +// RUN: not %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ +// RUN: -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s apazos

[PATCH] D93585: [AArch64][Clang][Linux] Enable out-of-line atomics by default.

t.p.northover added a comment. I think this looks good now, modulo Sjoerd's last comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93585/new/ https://reviews.llvm.org/D93585 ___ cfe-commits mailing

[PATCH] D95228: Add swift_async_context parameter attribute mapping to IR equivalent

t.p.northover created this revision. Herald added subscribers: dexonsmith, jdoerfert, mcrosier. Herald added a reviewer: aaron.ballman. t.p.northover requested review of this revision. This adds `__attribute__((swift_async_context))` very much following the existing `swift_context` so that

[PATCH] D93585: [AArch64] Enable out-of-line atomics by default.

t.p.northover added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64.td:1087 FeatureNEON, + FeatureOutlineAtomics, FeaturePerfMon, ilinpv wrote: > t.p.northover wrote: > > I think this

[PATCH] D93585: [AArch64] Enable out-of-line atomics by default.

t.p.northover added inline comments. Comment at: clang/include/clang/Driver/ToolChain.h:460 + /// Test whether this toolchain supports outline atomics by default. + virtual bool IsOADefault(const llvm::opt::ArgList ) const { +return false; This is a pretty

[PATCH] D92930: [Clang] Add vcmla and rotated variants for Arm ACLE.

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. That's a nice improvement. Still LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92930/new/ https://reviews.llvm.org/D92930

[PATCH] D92930: [Clang] Add vcmla and rotated variants for Arm ACLE.

t.p.northover added a comment. Looks fine to me except for one weird quirk that I don't think should be there. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5237 NEONMAP1(vcaddq_rot90_v, arm_neon_vcadd_rot90, Add1ArgType), + NEONMAP1(vcaddq_rot90_v, arm_neon_vcadd_rot90,

[PATCH] D89959: UBSAN: emit distinctive traps in trapping mode

t.p.northover closed this revision. t.p.northover added a comment. Committed: To github.com:llvm/llvm-project.git c54d827fdb12..c5978f42ec8e main -> main CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89959/new/ https://reviews.llvm.org/D89959

[PATCH] D91147: AArch64: classify Triple::aarch64_32 as AArch64

t.p.northover closed this revision. t.p.northover added a comment. Thanks Gerolf. Committed: To github.com:llvm/llvm-project.git ae9d96a656a1..152df3add156 master -> master CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91147/new/ https://reviews.llvm.org/D91147

[PATCH] D91147: AArch64: classify Triple::aarch64_32 as AArch64

t.p.northover updated this revision to Diff 305064. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91147/new/ https://reviews.llvm.org/D91147 Files: clang/lib/Driver/ToolChain.cpp clang/test/Driver/frame-pointer-elim.c llvm/include/llvm/ADT/Triple.h

[PATCH] D91147: AArch64: classify Triple::aarch64_32 as AArch64

t.p.northover added inline comments. Comment at: clang/lib/Driver/ToolChain.cpp:1066 if (getTriple().getArch() == llvm::Triple::x86_64 || - getTriple().isAArch64() || getTriple().isRISCV()) + (getTriple().isAArch64() && getTriple().isArch64Bit()) || +

[PATCH] D91157: [AArch64] Out-of-line atomics (-moutline-atomics) implementation.

t.p.northover added inline comments. Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2170 + SmallVector Ops; + if (TLI.getLibcallName(LC)) { +Ops.append(Node->op_begin() + 2, Node->op_end()); jyknight wrote: > t.p.northover wrote: > > I

[PATCH] D91157: [AArch64] Out-of-line atomics (-moutline-atomics) implementation.

t.p.northover added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:6366 + // Option -moutline-atomics supported for AArch64 target only. + if (Triple.getArch() != llvm::Triple::aarch64) { +

[PATCH] D91147: AArch64: classify Triple::aarch64_32 as AArch64

t.p.northover created this revision. Herald added subscribers: dexonsmith, danielkiss, s.egerton, simoncook, hiraditya, kristof.beyls, mcrosier. Herald added a project: LLVM. t.p.northover requested review of this revision. We want `arm64_32` to omit leaf frame pointers. At the moment this is

[PATCH] D89959: UBSAN: emit distinctive traps in trapping mode

t.p.northover added inline comments. Comment at: llvm/include/llvm/IR/Intrinsics.td:1242 +def int_ubsantrap : Intrinsic<[], [llvm_i8_ty], + [IntrNoReturn, IntrCold, ImmArg>]>; jdoerfert wrote: > should this be readonly and

[PATCH] D89959: UBSAN: emit distinctive traps in trapping mode

t.p.northover marked an inline comment as done. t.p.northover added a comment. > Was this measured with all of -fsanitize=undefined enabled? If so, the actual > size overhead is likely lower, as only a subset of these checks get enabled > in production settings. Yes, I used

[PATCH] D89959: UBSAN: emit distinctive traps in trapping mode

t.p.northover added a comment. With current CodeGen by the time you reach the trap you have no idea what came before so I think you'd still need a separate trap instruction per failure kind. So the Clang and generic LLVM side would be unaffected. I suppose on X86 it could save a few bytes in

[PATCH] D87095: [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth.

t.p.northover added a comment. I had a look through this and everything seemed to be in place. I think the ABI versioning is probably sufficient to prevent surprises and land this now, to avoid churn in the rest of the code. If more is really needed, we could add a temporary warning

[PATCH] D80911: AArch64+ARM: make LLVM consider system registers volatile to prevent unsound optimizations.

t.p.northover closed this revision. t.p.northover added a comment. Thanks. Pushed to master as 5165b2b5fd5 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80911/new/

[PATCH] D80911: AArch64+ARM: make LLVM consider system registers volatile to prevent unsound optimizations.

t.p.northover added a comment. Herald added a reviewer: jdoerfert. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80911/new/ https://reviews.llvm.org/D80911 ___ cfe-commits mailing list

[PATCH] D80911: AArch64+ARM: make LLVM consider system registers volatile to prevent unsound optimizations.

t.p.northover created this revision. Herald added subscribers: danielkiss, jdoerfert, asbirlea, hiraditya, kristof.beyls, mcrosier. Herald added projects: clang, LLVM. Some of the system registers readable on AArch64 & ARM platforms return different values with each read (for example a timer

[PATCH] D80910: AArch64+ARM: make LLVM consider system registers volatile to prevent unsound optimizations.

t.p.northover abandoned this revision. t.p.northover added a comment. Sorry. Keyboard decided to create diff before I'd filled everything in. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80910/new/ https://reviews.llvm.org/D80910

[PATCH] D80910: AArch64+ARM: make LLVM consider system registers volatile to prevent unsound optimizations.

t.p.northover created this revision. Herald added subscribers: llvm-commits, cfe-commits, danielkiss, jdoerfert, asbirlea, hiraditya, kristof.beyls, mcrosier. Herald added projects: clang, LLVM. t.p.northover abandoned this revision. t.p.northover added a comment. Sorry. Keyboard decided to

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover closed this revision. t.p.northover added a comment. Thanks Ahmed, pushed: To github.com:llvm/llvm-project.git 0a4daff6e26f..903e5c3028d6 master -> master CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70779/new/ https://reviews.llvm.org/D70779

[PATCH] D71723: ConstrainedFP: use API compatible with opaque pointers.

t.p.northover closed this revision. t.p.northover added a comment. Thanks Kevin. Committed as 85cb560b8a4 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71723/new/

[PATCH] D71723: ConstrainedFP: use API compatible with opaque pointers.

t.p.northover created this revision. t.p.northover added a reviewer: kpn. Herald added a subscriber: mcrosier. Herald added projects: clang, LLVM. This just updates an IRBuilder interface to take Functions instead of Values so the type can be derived, and fixes some callsites in Clang to call

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover updated this revision to Diff 231872. t.p.northover added a comment. Stop inheriting CPU features because they aren't necessarily strictly monotonic. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70779/new/ https://reviews.llvm.org/D70779 Files:

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover marked an inline comment as done. t.p.northover added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64.td:587 +"Apple A10", [ +ProcAppleA7, +

[PATCH] D70862: [ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-A

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. > Why are you only implementing rot90 and rot270 intrinsics? My quick > calculations made rot0 and rot90 the natural ones to implement a bog-standard > complex multiplication,

[PATCH] D70862: [ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-A

t.p.northover added a comment. Why are you only implementing rot90 and rot270 intrinsics? My quick calculations made rot0 and rot90 the natural ones to implement a bog-standard complex multiplication, but even if I slipped up there I'd expect the others to be useful in some situations.

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover marked an inline comment as done. t.p.northover added a comment. Thanks Florian. I'll wait as you suggest. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:143 MtuneLowerCase = llvm::sys::getHostCPUName(); - if (MtuneLowerCase == "cyclone") { + if

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover updated this revision to Diff 231220. t.p.northover added a comment. Test updates after switching arm64_32 default CPU to apple-s4. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70779/new/ https://reviews.llvm.org/D70779 Files:

[PATCH] D70779: AArch64: add support for newer Apple CPUs

t.p.northover created this revision. t.p.northover added a reviewer: ab. Herald added subscribers: hiraditya, kristof.beyls, mcrosier. Herald added a project: LLVM. t.p.northover updated this revision to Diff 231220. t.p.northover added a comment. Test updates after switching arm64_32 default CPU

[PATCH] D69618: NeonEmitter: clean up prototype modifiers

t.p.northover added a comment. Sorry about the delay investigating this, your e-mail bypassed my inbox for some reason and I only noticed the issue when Hans reverted the change this afternoon. I'm looking into it now. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69618/new/

[PATCH] D55562: Atomics: support min/max orthogonally

t.p.northover closed this revision. t.p.northover added a comment. Thanks JF. Finally pushed it today: To github.com:llvm/llvm-project.git 9f3fdb0d7fab..5cf58768cb3b master -> master Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D55562/new/

[PATCH] D69618: NeonEmitter: clean up prototype modifiers

t.p.northover closed this revision. t.p.northover marked 2 inline comments as done. t.p.northover added a comment. Thanks. Pushed it with those suggestions: To github.com:llvm/llvm-project.git c34478f5f6c7..3f91705ca54b master -> master CHANGES SINCE LAST ACTION

[PATCH] D63131: arm64_32: implement the desired ABI for the ILP32 triple.

t.p.northover marked 6 inline comments as done. t.p.northover added a comment. Thanks, I've updated for most of the suggestions and committed it. I'll make the AArch64 naming changes separately if we decide to. Comment at: clang/lib/Basic/Targets/AArch64.cpp:167 // Target

[PATCH] D69618: NeonEmitter: clean up prototype modifiers

t.p.northover added a comment. Ping. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69618/new/ https://reviews.llvm.org/D69618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D67436: CodeGen: set correct result for atomic compound expressions

t.p.northover closed this revision. t.p.northover added a comment. Thanks JF. To github.com:llvm/llvm-project.git 0ec6a4882ee..10e0d64337d master -> master > Separately, does this do floating-point add / sub properly? We added them too > C++20. It looks like that already works because it

[PATCH] D69716: NeonEmitter: remove special 'a' modifier.

t.p.northover closed this revision. t.p.northover added a comment. Thanks: To github.com:llvm/llvm-project.git 6c2a4f5ff93..59f063b89c5 master -> master Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69716/new/ https://reviews.llvm.org/D69716

[PATCH] D69715: NeonEmitter: change Type representation. NFC.

t.p.northover closed this revision. t.p.northover added a comment. > I guess the extra checks are due to existing code "accidentally" doing the > right thing? Yep, they were helpful while I was in the process of converting (in the end I went via `AAAFloating` enumerators to make sure all uses

[PATCH] D69716: NeonEmitter: remove special 'a' modifier.

t.p.northover created this revision. t.p.northover added a reviewer: efriedma. Herald added a subscriber: mcrosier. Herald added a project: clang. This has been separated off from D69618 to reduce diff clutter, as it really stands on its own. The 'a' modifier is

[PATCH] D69715: NeonEmitter: change Type representation. NFC.

t.p.northover created this revision. t.p.northover added a reviewer: efriedma. Herald added a subscriber: mcrosier. Herald added a project: clang. This has been separated off from D69618 to reduce clutter. Instead of using a sequence of bools to describe whether

[PATCH] D69618: NeonEmitter: clean up prototype modifiers

t.p.northover added a comment. > It looks like this patch contains a few other changes, besides the changes to > the prototypes. In particular, the change to CGBuiltin.cpp, and there are a > few new lines in the .td files that don't correspond to anything in the old > versions. Is that

[PATCH] D63131: arm64_32: implement the desired ABI for the ILP32 triple.

t.p.northover updated this revision to Diff 225259. t.p.northover added a comment. Updating diff. How target features are handled changed slightly upstream. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63131/new/ https://reviews.llvm.org/D63131

[PATCH] D63131: arm64_32: implement the desired ABI for the ILP32 triple.

t.p.northover added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63131/new/ https://reviews.llvm.org/D63131 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D67436: CodeGen: set correct result for atomic compound expressions

t.p.northover added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67436/new/ https://reviews.llvm.org/D67436 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D67436: CodeGen: set correct result for atomic compound expressions

t.p.northover created this revision. Herald added subscribers: jfb, mcrosier. Herald added a project: clang. Atomic compound expressions try to use atomicrmw if possible, but this path doesn't set the `Result` variable, leaving it to crash in later code if anything ever tries to use the result

[PATCH] D55562: Atomics: support min/max orthogonally

t.p.northover added a comment. Ping. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D55562/new/ https://reviews.llvm.org/D55562 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D65582: IR: accept and print numbered %N names for function args

t.p.northover accepted this revision. t.p.northover marked an inline comment as done. t.p.northover added a comment. Thanks Reid, committed as r367755. Comment at: llvm/utils/add_argument_names.py:5 +def fix_string(s): +TYPE =

[PATCH] D64416: [AArch64] Add support for Transactional Memory Extension (TME)

t.p.northover added inline comments. Comment at: clang/test/Sema/aarch64-tme-errors.c:1 +// RUN: %clang_cc1 -triple aarch64-eabi -verify %s + I don't think the Sema checks need to be split over so many files. One for the whole of transactional seems enough.

[PATCH] D63131: arm64_32: implement the desired ABI for the ILP32 triple.

t.p.northover created this revision. t.p.northover added a reviewer: fhahn. Herald added subscribers: jfb, kristof.beyls, javed.absar, mcrosier. Herald added a project: clang. This adds all of the ABI tweaks we need to match the arm64_32 ABI as it exists in the wild. Most cirtically, of course,

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover marked an inline comment as done. t.p.northover added a comment. Thanks for the suggestion Florian, and sorry it's taken so long to act on it. I've split the patch up as you suggest, I'll make this one cover the Triple bits. Comment at:

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover updated this revision to Diff 204009. t.p.northover added a comment. This diff now only covers the trivial additions so that "arm64_32" is understood by the driver and creates AArch64 instantiations of relevant classes. Code generated is still wildly incorrect (not even ILP32

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover added a comment. Ping. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61939/new/ https://reviews.llvm.org/D61939 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover added a comment. Oops, yes. I'll leave it wrong though, the best that could come out of any attempt to change it would be to split the thread on llvm-commits. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61939/new/ https://reviews.llvm.org/D61939

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover updated this revision to Diff 200707. t.p.northover added a comment. During upstreaming we've changed from detecting an "arm64_32" ArchName to using a Triple::aarch64_32 Arch. We recently discovered a bug that meant only AArch32 NEON types were permitted, which is fixed in this

[PATCH] D61939: AArch64: add support for arm64_23 (ILP32) IR generation

t.p.northover created this revision. Herald added subscribers: jfb, kristof.beyls, javed.absar, mcrosier. Herald added a project: clang. This patch implements the arm64_32 ABI used in watchOS from the Clang side. It's mostly pretty straightforward since it's so close to normal AArch64: handle

[PATCH] D55562: Atomics: support min/max orthogonally

t.p.northover updated this revision to Diff 198452. t.p.northover added a comment. Sorry, I managed to forget about this one somehow. I hadn't changed the 32-bit requirement, but I agree it shouldn't be there so this diff removes it and adds tests for the newly legal cases. Repository: rC

[PATCH] D60485: [AArch64] Add support for MTE intrinsics

t.p.northover accepted this revision. t.p.northover added inline comments. This revision is now accepted and ready to land. Comment at: lib/CodeGen/CGBuiltin.cpp:7129-7131 +// Although it is possible to supply a different return +// address (first arg) to this intrinsic,

[PATCH] D60485: [AArch64] Add support for MTE intrinsics

t.p.northover added inline comments. Comment at: include/clang/Sema/Sema.h:10762 bool AllowName); + bool SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall); public: Slightly misaligned.

[PATCH] D60719: Demonstrate how to fix freestanding for memcpy

t.p.northover added a comment. > IIUC freestanding environment should not rely on memcpy being present so my > take on it was that by "fixing" freestanding I could have my cake and eat it > too. The formal situation is that freestanding implementations are only required to provide language

[PATCH] D60719: Demonstrate how to fix freestanding for memcpy

t.p.northover added a comment. I think it'd be pretty unpopular with the people I know who use freestanding. They're mostly working on microcontrollers and compiling -Oz so the extra code size would be untenable; they also have memcpy implementations anyway because they use it in their own

[PATCH] D60697: [ARM] Allow "-march=foo+fp" to vary with foo.

t.p.northover added inline comments. Comment at: llvm/lib/Support/ARMTargetParser.cpp:476 -StringRef ARM::getArchExtFeature(StringRef ArchExt) { - if (ArchExt.startswith("no")) { -StringRef ArchExtBase(ArchExt.substr(2)); -for (const auto AE : ARCHExtNames) { -

[PATCH] D60709: [ARM] Support inline assembler constraints for MVE.

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. Excellent, looks good to me then. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60709/new/ https://reviews.llvm.org/D60709

[PATCH] D60699: [ARM] add CLI support for 8.1-M and MVE.

t.p.northover accepted this revision. t.p.northover added a comment. This revision is now accepted and ready to land. This looks good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60699/new/ https://reviews.llvm.org/D60699

[PATCH] D60697: [ARM] Allow "-march=foo+fp" to vary with foo.

t.p.northover added a comment. This needs some tests. I'm also not quite sure when you'd use bare "+fp", if it's the default anyway. Comment at: llvm/lib/Support/ARMTargetParser.cpp:476 -StringRef ARM::getArchExtFeature(StringRef ArchExt) { - if (ArchExt.startswith("no"))

[PATCH] D60691: [ARM] Replace fp-only-sp and d16 with fp64 and d32.

t.p.northover added a comment. I like the direction of this change, and the details look correct too. The one thing I wonder about is whether we should be upgrading .bc files too (or otherwise support fp-only-sp in legacy inputs). I think it's a specialized enough feature that there won't be

[PATCH] D60710: [ARM] Add ACLE feature macros for MVE.

t.p.northover added a comment. Could you add some tests? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60710/new/ https://reviews.llvm.org/D60710 ___ cfe-commits mailing list

[PATCH] D60709: [ARM] Support inline assembler constraints for MVE.

t.p.northover added a comment. Is this coordinated with GCC? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60709/new/ https://reviews.llvm.org/D60709 ___ cfe-commits mailing list

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