[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/sdesmalen-arm approved this pull request. https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // bitcast. if (const auto *FixedSrc = dyn_cast(SrcTy)) { if (const auto *ScalableDst = dyn_cast(DstTy)) { -// If we are casting a fixed i8 vector to a scalable 16 x i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/5] [IRGen][AArch64][RISCV] Generalize bitcast between i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/4] [IRGen][AArch64][RISCV] Generalize bitcast between i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -70,13 +70,17 @@ fixed_float64m1_t call_float64_ff(fixed_float64m1_t op1, fixed_float64m1_t op2) // CHECK-LABEL: @call_bool1_ff( // CHECK-NEXT: entry: -// CHECK-NEXT:[[SAVED_VALUE4:%.*]] = alloca , align 8 -// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 8

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // bitcast. if (const auto *FixedSrc = dyn_cast(SrcTy)) { if (const auto *ScalableDst = dyn_cast(DstTy)) { -// If we are casting a fixed i8 vector to a scalable 16 x i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

topperc wrote: > Generalising this code makes sense, 16 should never have been hardcoded here. > > Is it possible to add a test for the case where the predicate type is not > ``? I rebased, which picked up more tests that are affected for RISC-V. This also pointed out that I missed very

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/3] [IRGen][AArch64][RISCV] Generalize bitcast between i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76548 >From 3dfa00b0dab1820d1d8692ea91e98b29c9f8b627 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:49:03 -0800 Subject: [PATCH 1/2] [IRGen][AArch64][RISCV] Generalize bitcast between i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/sdesmalen-arm commented: Generalising this code makes sense, 16 should never have been hardcoded here. Is it possible to add a test for the case where the predicate type is not ``? > Though I do wonder if we have the bitcast on the wrong side. Maybe we should > be casting

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // bitcast. if (const auto *FixedSrc = dyn_cast(SrcTy)) { if (const auto *ScalableDst = dyn_cast(DstTy)) { -// If we are casting a fixed i8 vector to a scalable 16 x i1

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

llvmbot wrote: @llvm/pr-subscribers-clang-codegen Author: Craig Topper (topperc) Changes Instead of only handling vscale x 16 x i1 predicate vectors, handle any scalable i1 vector where the known minimum is divisible by 8. This will be used on RISC-V where we have multiple sizes of

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/76548 Instead of only handling vscale x 16 x i1 predicate vectors, handle any scalable i1 vector where the known minimum is divisible by 8. This will be used on RISC-V where we have multiple sizes of predicate types.