[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105834/new/ https://reviews.llvm.org/D105834

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105501/new/ https://reviews.llvm.org/D105501

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added a comment. The testing is a bit overkill. A single test case with run lines for `-mcpu=pwr7-10` and a single prefix for each should suffice. For each prefix, just check for `+/-` for all the features you expect. The triples can be randomly distributed across the 4 run lines. And

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I believe that your failing test case is because you are attempting to emit code for these builtins in the target independent code and the values just happen to match up.

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3275 -static bool SemaFeatureCheck(Sema , CallExpr *TheCall, - StringRef FeatureToCheck, unsigned DiagID) { +static bool SemaArchFeatureCheck(Sema , CallExpr *TheCall, +

[PATCH] D105666: [PowerPC] [Altivec] Use signed comparison for vec_all_* and vec_any_* interfaces that compare vector bool types with vector signed types

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105666/new/ https://reviews.llvm.org/D105666

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1535 - def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">, - Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>; } lkail wrote: > Just curious,

[PATCH] D105236: [PowerPC] Implement Load and Reserve and Store Conditional Builtins

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1533 + def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; + def int_ppc_ldarx :

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. LGTM. @NeHuang please have a look to see if your comments are adequately addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103668/new/ https://reviews.llvm.org/D103668

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1733 +// as XL produces a tweq , . +def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31), + (TD 4,

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll:135 +; CHECK: # %bb.0: +; CHECK-NEXT:twnei 3, 0 +; CHECK-NEXT:blr Where are the aliases `twnei` and `tdnei` coming from? You don't seem to add

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. It appears that Victor's comments have not been addressed yet and this is not ready for the next round of review. Requesting changes again to take it out of the queue until

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added a comment. Can you please add a test for this similar to `clang/test/Driver/ppc-pcrel.cpp` and other similar tests? Also, I imagine this will produce some warnings from the back end since the back end doesn't know what these target features mean. Can you please see what happens

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a small nit. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc

[PATCH] D105236: [PowerPC] Implament Atomic Load and Stores Builtins

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724 + +let Predicates = [HasP8Altivec] in { + def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A), lkail wrote: > IIRC, `l(w|d)arx`, `st(w|d)cx` are supported very early and don't

[PATCH] D103615: [Clang] Add option for vector compare compatibility.

nemanjai added a comment. I haven't had time to review this yet, but I just wanted to chime in on the option spelling and description. I think we should go with: -faltivec-src-compat={xl|gcc|mixed} Source-level compatibility for Altivec vectors (for PowerPC targets). This includes

[PATCH] D103386: [PowerPC] Fix x86 vector intrinsics wrapper compilation under C++

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for fixing this. Comment at: clang/lib/Headers/ppc_wrappers/xmmintrin.h:31 use vector SIMD operations. We recommend this for new applications. */

[PATCH] D103125: [Clang][WIP] Allow renaming of "clang"

nemanjai abandoned this revision. nemanjai added a comment. Thanks everyone for providing feedback on this. I posted this to gauge interest in the community for such a change. As it appears, the consensus seems to be that this isn't desired so I will abandon this change and vendors will

[PATCH] D103235: [SPE] Disable strict-fp for SPE by default

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103235/new/ https://reviews.llvm.org/D103235

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for implementing this. The redundant pseudo can be removed when committing. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2572 +

[PATCH] D103125: [Clang][WIP] Allow renaming of "clang"

nemanjai created this revision. nemanjai added reviewers: rjmccall, rsmith, craig.topper, t.p.northover, arsenm, kparzysz, echristo. Herald added subscribers: usaxena95, s.egerton, kadircet, arphaman, delcypher, simoncook, mgorny. nemanjai requested review of this revision. Herald added

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

nemanjai added subscribers: rjmccall, rsmith. nemanjai added a comment. In terms of the motivation for this, the description of the patch should include something along the lines of: "This is the first in a series of patches to provide builtins for compatibility with the XL compiler." Since

[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102191/new/ https://reviews.llvm.org/D102191

[PATCH] D92815: [PowerPC] [Clang] Enable float128 feature on VSX targets

nemanjai added a comment. Looks like this is causing failures at https://lab.llvm.org/buildbot/#/builders/76/builds/2422 Please revert. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92815/new/ https://reviews.llvm.org/D92815

[PATCH] D102064: Parse vector bool when stdbool.h and altivec.h are included

nemanjai added a comment. This seems fine to me now but I'll defer to front end experts for approval. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102064/new/ https://reviews.llvm.org/D102064 ___

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Maybe give this a couple of days to see if any other reviewers have further input. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100782/new/ https://reviews.llvm.org/D100782 ___ cfe-commits mailing list

[PATCH] D100604: [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100604/new/ https://reviews.llvm.org/D100604 ___ cfe-commits mailing list

[PATCH] D92815: [PowerPC] [Clang] Enable float128 feature on VSX targets

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Comment at: clang/lib/Basic/Targets/PPC.cpp:359 llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { -// We have __float128 on PPC but not power

[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Please add the missing BE handling. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2800 + (f32 (fpround f64:$A)), (f32

[PATCH] D102064: Parse vector bool when stdbool.h and altivec.h are included

nemanjai added inline comments. Comment at: clang/test/Parser/altivec-bool.c:11 +// RUN:-target-feature +altivec -fsyntax-only %s + +__vector bool char bc; Do we not want the test case to provide a similar define to what `stdbool.h` does?

[PATCH] D100482: [PowerPC] Provide MMA builtins for compatibility

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for fixing this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100482/new/ https://reviews.llvm.org/D100482

[PATCH] D101209: [PowerPC] Provide fastmath sqrt and div functions in altivec.h

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc3da07d216dd: [PowerPC] Provide fastmath sqrt and div functions in altivec.h (authored by nemanjai). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2798 + (f32 (fpround f64:$A)), (f32 (fpround f64:$A, + (v4f32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSP f64:$A), VSRC), 0))>; def : Pat<(v4f32 (build_vector

[PATCH] D101209: [PowerPC] Provide fastmath sqrt and div functions in altivec.h

nemanjai updated this revision to Diff 341456. nemanjai added a comment. Changed `rsqrt` to be an actual reciprocal rather than just a refined `sqrt` estimate. I have verified that the code generated is equivalent to gcc's and the results produced are the same. Repository: rG LLVM Github

[PATCH] D101209: [PowerPC] Provide fastmath sqrt and div functions in altivec.h

nemanjai added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15130 + Value *Y = EmitScalarExpr(E->getArg(1)); + auto Ret = Builder.CreateFDiv(X, Y, "recipdiv"); + Builder.setFastMathFlags(FMF); bmahjour wrote: > I wonder if we can

[PATCH] D100482: [PowerPC] Provide MMA builtins for compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. There may be something I am overlooking here, but I really don't think we need to or want to change the back end. Just add the new builtins to the front end as aliases to the

[PATCH] D101209: [PowerPC] Provide fastmath sqrt and div functions in altivec.h

nemanjai added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15122 + case PPC::BI__builtin_ppc_rsqrtd: { +auto FMF = Builder.getFastMathFlags(); +Builder.getFastMathFlags().setFast(); qiucf wrote: > Seems FMF will be automatically

[PATCH] D79714: [Diagnostics] Restore -Wdeprecated warning when user-declared copy assignment operator is defined as deleted (PR45634)

nemanjai added a comment. The fixes in https://reviews.llvm.org/D101214 are sufficient to bring the -Werror bootstrap back to green. Please review the patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79714/new/ https://reviews.llvm.org/D79714

[PATCH] D101214: Disable deprecated-copy warnings on various LLVM code to bring the bot back to green

nemanjai created this revision. nemanjai added reviewers: xbolva00, rsmith. nemanjai requested review of this revision. Herald added projects: clang, LLVM. Herald added a subscriber: llvm-commits. Bootstrap with `-Werror` is currently broken due to https://reviews.llvm.org/D79714. This patch is

[PATCH] D79714: [Diagnostics] Restore -Wdeprecated warning when user-declared copy assignment operator is defined as deleted (PR45634)

nemanjai added a comment. In D79714#2713610 , @xbolva00 wrote: > I pushed a fix to just disable this warning for googlemock/gtest. There are still more of these. I will apply the same fix to `utils/unittest/googlemock/include/gmock/gmock.h` unless you

[PATCH] D101209: [PowerPC] Provide fastmath sqrt and div functions in altivec.h

nemanjai created this revision. nemanjai added reviewers: cebowleratibm, bmahjour, PowerPC. Herald added subscribers: shchenz, kbarton. nemanjai requested review of this revision. Herald added a project: clang. This adds the long overdue implementations of these functions that have been part of

[PATCH] D101130: [PowerPC] Provide XL-compatible builtins in altivec.h

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG19b29b1ed1ba: [PowerPC] Provide XL-compatible builtins in altivec.h (authored by nemanjai). Changed prior to commit:

[PATCH] D79714: [Diagnostics] Restore -Wdeprecated warning when user-declared copy assignment operator is defined as deleted (PR45634)

nemanjai added a comment. This breaks Clang's ability to bootstrap LLVM with `-Werror` as evidenced by the buildbot failure https://lab.llvm.org/buildbot/#/builders/36/builds/7587. Please revert or fix the `googletest` code that trips this warning. Pertinent file: FAILED:

[PATCH] D101130: [PowerPC] Provide XL-compatible builtins in altivec.h

nemanjai added inline comments. Comment at: clang/lib/Headers/altivec.h:3055 +#ifdef __XL_COMPAT_ALTIVEC__ +/* vec_ctf */ jsji wrote: > This only affects __VSX__ version right? If so, can we move `#ifdef > __XL_COMPAT_ALTIVEC__` into `#ifdef __VSX__`？ > Or

[PATCH] D101130: [PowerPC] Provide XL-compatible builtins in altivec.h

nemanjai created this revision. nemanjai added reviewers: cebowleratibm, hubert.reinterpretcast, bmahjour, PowerPC. Herald added subscribers: shchenz, kbarton. nemanjai requested review of this revision. Herald added a project: clang. There are some interfaces in altivec.h that are not

[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This will still produce a redundant `XXSLDWI`: vector float test(vector float a, float b) { a[3] = b; return a; } when compiled with `-mcpu=pwr9`. Repository: rG

[PATCH] D100933: [clang] Recognize ppc32 as valid mcpu value

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100933/new/ https://reviews.llvm.org/D100933

[PATCH] D98546: [PowerPC] Add __PCREL__ when PC Relative is enabled.

nemanjai added a comment. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98546/new/ https://reviews.llvm.org/D98546 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Thank you for your patience. LGTM now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96265/new/ https://reviews.llvm.org/D96265

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Can you please merge the tests into one file. There is no compelling reason to split them up and it is more difficult to review and make sense of what is going on. The test case

[PATCH] D95634: [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM as long as the nits are addressed on the commit. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8611 Subtarget.hasPrefixInstrs()) { -if

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90173/new/ https://reviews.llvm.org/D90173 ___ cfe-commits mailing list

[PATCH] D92080: [Clang] Mutate long-double math builtins into f128 under IEEE-quad

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. I think it would be useful to run a functional test with a toolchain that has these library functions. That shouldn't gate this change though. CHANGES SINCE LAST ACTION

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is still incorrect. The indices for the hi/low words are backwards. You can easily demonstrate this with a test case such as: a.c: vector double test() { return (vector

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

This revision was automatically updated to reflect the committed changes. Closed by commit rG3f7b4ce96065: [PowerPC] Add support for embedded devices with EFPU2 (authored by nemanjai). Changed prior to commit: https://reviews.llvm.org/D92935?vs=315119=316093#toc Repository: rG LLVM Github

[PATCH] D94162: [PowerPC] Add variants of 64-bit vector types for vec_sel.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Kind of bizarre that we missed these, thanks for adding them. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94162/new/

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

nemanjai added a comment. In D92935#2477171 , @kiausch wrote: > Regarding similar GCC options: > > AFAIK GCC has had the spe options -msingle-float and -mdouble-float until spe > support was dropped after version 8.3. > These options would kind of match

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. I don't really have any objections to this, but if there is a similar options to GCC, I would hope that they are the same. Please add a comment in the commit message to that end. Other

[PATCH] D93377: [Clang] Add __ibm128 type to represent ppc_fp128

nemanjai added a comment. Seems that conversion diagnostic test cases are completely missing. Comment at: clang/include/clang/Basic/TargetInfo.h:680 + /// Return the mangled code of __ibm128. + virtual const char *getIbm128Mangling() const { return "g"; } +

[PATCH] D92054: [Driver] Default Generic_GCC ppc/ppc64/ppc64le to -fasynchronous-unwind-tables

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Comment at: clang/test/Driver/ppc-features.cpp:45 +// PPC64: "-munwind-tables" +// PPC64-SAME: "-mfloat-abi" "hard" Curious - how come no

[PATCH] D90329: [PowerPC] Fix va_arg in C++, Objective-C on 32-bit ELF targets

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a minor nit. Comment at: clang/lib/CodeGen/TargetInfo.cpp:4722 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64; - bool isInt = - Ty->isIntegerType() ||

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is not functionally correct. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9345 + return DAG.getBitcast(Op.getValueType(), SplatNode); +

[PATCH] D92445: [PowerPC] Add powerpcle target.

nemanjai added a comment. This seems problematic to me for a few reasons: 1. There is no 32-bit toolchains or libraries for little endian Linux systems 2. There is no support in the ELFv2 ABI for 32-bit object mode and there may be a number of places we assume that little endian systems use

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list

[PATCH] D89986: [AIX]ignore the option -fvisibility-inlines-hidden when there is no option -fvisibility=*

nemanjai added inline comments. Comment at: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp:30-34 +// COMMON-ASM: mflr 0 +// COMMON-ASM-NEXT:stw 0, 8(1) +// COMMON-ASM-NEXT:stwu 1, -64(1) +// COMMON-ASM-NEXT:bl ._Z1fv +// NOP-ASM-NEXT: nop

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

nemanjai added inline comments. Comment at: llvm/include/llvm/Analysis/TargetLibraryInfo.h:91 Accelerate, // Use Accelerate framework. +LIBMVEC,// GLIBC Vector Math library. MASSV, // IBM MASS vector library. fpetrogalli wrote: > Can we

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-vsx.c:1 -// REQUIRES: powerpc-registered-target +// requires: powerpc-registered-target // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s

[PATCH] D82485: Add tests for sequences of callbacks that RecursiveASTVisitor produces

nemanjai added a comment. Hi @gribozavr do you think we can do something about this test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82485/new/ https://reviews.llvm.org/D82485 ___ cfe-commits mailing

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. The remaining requests can be fulfilled when committing. I don't think this requires another review. Thanks. Comment at: clang/lib/Headers/altivec.h:7865 +#endif +

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is not what we want. The builtin behaves correctly. It is equivalent to the generic `__builtin_copysign` and it would be very surprising to a user if it reverses the

[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

nemanjai added a comment. This clearly changes behaviour and should thereby not have the `[NFC]` tag. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D88105/new/ https://reviews.llvm.org/D88105 ___ cfe-commits mailing list

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for your patience and for addressing all the comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3165 +static bool isEltOfVectorTy(ASTContext , CallExpr *Call, Sema , +QualType VectorEltTy, QualType EltTy) { I think this should actually take a vector

[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

nemanjai added a comment. It turns out that the culprit for the PPC bot failures is actually https://reviews.llvm.org/rG144e57fc9535 But this just took a while to manifest. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87921/new/

[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

nemanjai added a comment. In D87921#2288686 , @morehouse wrote: > The revert did not fix the PPC bots. I suspect there is some kind of > resource issue from the logs: > > msgget:: No space left on device > sysmsg.c.tmp: >

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

nemanjai accepted this revision. nemanjai added a comment. The nits can be addressed when committing the code. LGTM otherwise. Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1452 // Vector Extend Sign -def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>; -def

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Just marking this not ready to keep my queue clean until the comments are addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14267 +assert((ArgWidth == 32 || ArgWidth == 64) && "Invalid argument width"); +if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt) + ConstArg *= ArgWidth / 8; `//

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai added a comment. Yes, this definitely needs a test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list

[PATCH] D87321: Fix -gz=zlib options for linker

nemanjai added a comment. This broke the PPC LLD bot and the failure has been ignored for 4 days. I believe it should be fixed with 3bc3983f229 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

nemanjai added inline comments. Comment at: clang/lib/Headers/altivec.h:7743 + return __builtin_altivec_vrlqnm(__a, ((__c << ShiftMask) | +(__b << ShiftRotation))); +} While correct, this implementation will require two

[PATCH] D82485: Add tests for sequences of callbacks that RecursiveASTVisitor produces

nemanjai added a comment. Is there a way this test case can somehow be broken up into multiple files? The test case takes a very long time to compile which causes intermittent but frequent failures on one of our bots that runs on a fairly small VM. Most of the failures listed here:

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a couple of minor nits. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13405 + // This combine is only eligible for a BUILD_VECTOR of v1i128. + // Other return types are not valid for the

[PATCH] D84291: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation

nemanjai accepted this revision. nemanjai added a comment. LGTM. The test case addition can be done on the commit. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. The description includes `... however it is more preferable to use bitcast`. It is not a question of preference but of correctness. The fp to int conversions truncate while

[PATCH] D81442: [PowerPC] Add clang options to control MMA support

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Since clang will now add `+/-mma` to the TargetFeatures list, please add a test case that specifies `-mattr=+/-mma` to `llc` to show that `llc` accepts it. Other than that, LGTM.

[PATCH] D83722: [PowerPC] Add options to control paired vector memops support

nemanjai added a comment. Please re-upload this and provide the missing context. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83722/new/ https://reviews.llvm.org/D83722 ___ cfe-commits mailing list

[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

nemanjai added a comment. @rzurob This cannot proceed without your approval since you requested changes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83497/new/ https://reviews.llvm.org/D83497 ___

[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a minor nit regarding the description. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:324 // P10 Vector Insert built-ins. -BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")

[PATCH] D80952: [FPEnv][Clang][Driver] Disable constrained floating point on targets lacking support.

nemanjai accepted this revision. nemanjai added a comment. As far as I'm concerned, this is fine for now. We can remove these once all in-tree target have implemented their support. LGTM but maybe give a couple of days for others to chime in. Comment at:

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks Amy. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80941/new/ https://reviews.llvm.org/D80941

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

nemanjai added a comment. Amy, I am really sorry. I initially did not read the description of the instructions in the ISA carefully. The semantics of these instructions are not actually `(op (and a, b))`. The mask is used to determine if a leading/trailing zero is counted or skipped. Take for

[PATCH] D80300: [Driver] Add DEFAULT_DYLD_PREFIX and DEFAULT_RPATH to complement DEFAULT_SYSROOT

nemanjai added a comment. According to https://clang.llvm.org/docs/CrossCompilation.html (under `Toolchain Options` option 2) it is quite likely that a user that desires to cross-compile will have the necessary toolchain installed into a directory that will not require the use of `--sysroot`.

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins in LLVM/Clang

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. In D80941#2066931 , @lebedev.ri wrote: > Why not lower it to `@llvm.cttz(and(a, b))`? That's a great idea. Particularly in the back end

[PATCH] D80374: [Clang] Enable KF and KC mode for [_Complex] __float128

This revision was automatically updated to reflect the committed changes. nemanjai marked an inline comment as done. Closed by commit rG9021ce9576e4: [Clang] Enable KF and KC mode for [_Complex] __float128 (authored by nemanjai). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D80533: [Clang] Enable _Complex __float

This revision was automatically updated to reflect the committed changes. Closed by commit rGf9e94eb8688d: [Clang] Enable _Complex __float128 (authored by nemanjai). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80533/new/

[PATCH] D80374: [Clang] Enable KF and KC mode for [_Complex] __float128

nemanjai marked 3 inline comments as done. nemanjai added inline comments. Comment at: clang/lib/Sema/SemaDeclAttr.cpp:3970 + DestWidth = 128; + break; case 'T': rjmccall wrote: > rjmccall wrote: > > Are there interactions with the other mode

[PATCH] D80374: [Clang] Enable KF and KC mode for [_Complex] __float128

nemanjai updated this revision to Diff 266820. nemanjai added a comment. Handled invalid uses of `KI` as there is no corresponding integer mode and added testing for it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80374/new/

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM aside from a couple of minor nits. Comment at: clang/lib/Basic/Targets/PPC.cpp:319 .Case("ppc64le", true) +

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