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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-07-09 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2381
+  if HasVV then {
+defvar suffix = !if(!or(HasVS, !eq(NAME, "vsm4r")), "vv", "v");
+// We don't need suffix in Zvkb extension since it's consider as normal

Why do we check `HasVS` when assigning suffix `vv`? I would have expected we 
use `HasVV`. In addition, why do we need to check `!eq(NAME, "vsm4r")` instead 
of setting the `HasVV` for that instruction?



Comment at: clang/include/clang/Basic/riscv_vector.td:2400
+// mnemonics into its intrinsic function name.
+defvar suffix = !if(!eq(NAME, "vgmul"), "vv", "vs");
+defvar name = NAME # !if(!or(IsZvkb, !or(!eq(NAME, "vaesz"),

Why not set `HasVS=1` and `HasVV=0` for `vaesz` instead of checking 
`!if(!eq(NAME, "vgmul"),...`?

Also, do you mean to be discussing `vaesz` in the comment but use `vgmul` below?


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-07-09 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

Can you please add a description for this patch?


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[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-30 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland accepted this revision.
michaelmaitland added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-25 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

In D149495#4373768 , @reames wrote:

> Let's go ahead and land this as is, we can rework the stylistic pieces once 
> the linked patches land.

This has landed in 
https://reviews.llvm.org/rG1a855819a87f426bdbd83c815fa47ca01fdf928f. I raised 
my question regarding examples in my previous comment on this post because I am 
starting to rework the stylistic concerns raised by @pcwang-thead.

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[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-25 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.

Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162
+  bool hasVInstructionsF16Mininal() const {
+return HasStdExtZvfhmin || HasStdExtZvfh;
+  }

michaelmaitland wrote:
> jacquesguan wrote:
> > craig.topper wrote:
> > > Doesn't HasStdExtZvfh already imply HasStdExtZvfhmin?
> > The v spec doesn't metion this.
> I think the spec conveys this when it says `The Zvfhmin extension depends on 
> the Zve32f extension.`
My mistake, that says `Zve32f`, not `Zvfh`. However, the spec does say:

`When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w 
instructions become defined when SEW=16` and also says `When the Zvfh extension 
is implemented, all instructions in Sections Vector Floating-Point 
Instructions.` Since `vfwcvt.f.f.v and vfncvt.f.f.w` are part of `Vector 
Floating-Point Instructions` section, this is how it is implied.

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[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-25 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162
+  bool hasVInstructionsF16Mininal() const {
+return HasStdExtZvfhmin || HasStdExtZvfh;
+  }

jacquesguan wrote:
> craig.topper wrote:
> > Doesn't HasStdExtZvfh already imply HasStdExtZvfhmin?
> The v spec doesn't metion this.
I think the spec conveys this when it says `The Zvfhmin extension depends on 
the Zve32f extension.`


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[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

In D150253#4355730 , @jacquesguan 
wrote:

> @michaelmaitland , I update this revision with my local branch. May you have 
> a look and see what missed compared with you version?

I have left some comments on the clang side of this patch, but I think you are 
pretty close and have that under control.

I will take a closer look on what is left to do on the CodeGen side of things 
this week, and I will let you know if I have any comments and if I think there 
is any opportunity to collaborate here.

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[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c:15
+
+
+

Do we need a test that checks calls to `__riscv_vfwcvt_f` and 
`__riscv_vfncvt_f` using type `vfloat16m1_t` without zvfh nor zvfhmin lead to 
the expected error asking for `zvfh or zvfhmin`?


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[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1856
   def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
-  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+  let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;

michaelmaitland wrote:
> In general, I believe that `vfwcvt_f_f_v` and `vfncvt_f_f_w` do not require 
> Zvfhmin or Zvfh. The only time that these intrinsics require Zvfhmin or Zvfh 
> is when the operands to these intrinsics have EEW=16.
The semantics for `RequiredFeatures` is `Features required to enable for this 
builtin.` Since not all types in the range require the ZvfhminOrZvfh feature, 
it may make sense to do some refactoring:

I think two possible solutions are:
  1. to split def of `vfwcvt_f_f_v` and `vfncvt_f_f_w ` by type_range and the 
type range `x` uses the RequiredFeatures
  2. Use different required features for different type ranges (i.e. 
RequiredFeatures is a list of lists where the outer list is for each type in 
the range, and the inner list is the RequiredFeature for that type.)


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[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: clang/lib/Sema/Sema.cpp:2049
+!TI.hasFeature("experimental-zvfhmin"))
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
 if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&

michaelmaitland wrote:
> Should this output `zvfhmin` instead of `zvfh` when `experimental-zvfhmin` 
> feature is not included?
Or maybe it makes more sense to change `"zvfh"` to `"zvfh or zvfhmin"`?


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[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1856
   def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
-  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+  let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;

In general, I believe that `vfwcvt_f_f_v` and `vfncvt_f_f_w` do not require 
Zvfhmin or Zvfh. The only time that these intrinsics require Zvfhmin or Zvfh is 
when the operands to these intrinsics have EEW=16.



Comment at: clang/lib/Sema/Sema.cpp:2049
+!TI.hasFeature("experimental-zvfhmin"))
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
 if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&

Should this output `zvfhmin` instead of `zvfh` when `experimental-zvfhmin` 
feature is not included?


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[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.

michaelmaitland wrote:
> pcwang-thead wrote:
> > So, are we going to discard `LMULXXXImpl` below?
> I will use `LMULXXXImpl` in a follow up NFC patch. This code below comes from 
> before `LMULXXXImpl` was introduced.
Can you please provide an example of how you intend on this being used today? I 
think it depends on https://reviews.llvm.org/D146198 since if we use 
`LMULXXXImpl` today, there is no way to differentiate behavior based on LMUL.


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[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1a855819a87f: [RISCV] Add support for V extenstion in 
SiFive7 (authored by michaelmaitland).

Changed prior to commit:
  https://reviews.llvm.org/D149495?vs=521024=521031#toc

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Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  defvar LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  defvar LLMUL = LargestLMUL.r;
+  defvar SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+// Cycles for segmented loads and stores are calculated using the
+// formula ceil(2 * nf * lmul).
+class SiFive7GetCyclesSegmented {
+  int c = !cond(
+!eq(mx, "M1") : !mul(!mul(2, nf), 1),
+!eq(mx, "M2") : !mul(!mul(2, nf), 2),
+!eq(mx,

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.

pcwang-thead wrote:
> So, are we going to discard `LMULXXXImpl` below?
I will use `LMULXXXImpl` in a follow up NFC patch. This code below comes from 
before `LMULXXXImpl` was introduced.


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[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 521024.
michaelmaitland marked 2 inline comments as done.
michaelmaitland added a comment.

Use defvar in subroutines.


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Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  defvar LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  defvar LLMUL = LargestLMUL.r;
+  defvar SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+// Cycles for segmented loads and stores are calculated using the
+// formula ceil(2 * nf * lmul).
+class SiFive7GetCyclesSegmented {
+  int c = !cond(
+!eq(mx, "M1") : !mul(!mul(2, nf), 1),
+!eq(mx, "M2") : !mul(!mul(2, nf), 2),
+!eq(mx, "M4") : !mul(!mul(2, nf), 4),
+!eq(mx, "M8") : !mul(!mul(2, nf), 8),
+// We can calculate ceil(a/b) using (a + b - 1) / b.
+// Since the

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-09 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:15
+class SiFive7IsWorstCaseMX MxList> {
+  string LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);

pcwang-thead wrote:
> I think I have fixed the issue that `defar` can't refer to template arguments 
> in D148197. So `LMUL`, `SSEW` and other fields can be replaced with `defvar`s.
A `defvar` statement defines a global variable. `SiFive7IsWorstCaseMX.c` becomes invalid syntax since `c` is not a member of 
`SiFive7IsWorstCaseMX` now that `c` is global. If we did use `defvar` here and 
gave `c` a more unique name so that it could fit in the global space, then we 
would also need to complicate it by adding a `MXxxx_MxListxxx` suffix for all 
`mx` and `SchedMxList` pairs. 

I think we'd like to keep these as `Type Iden = Value;`. What do you think?


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[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-09 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 520847.
michaelmaitland marked an inline comment as done.
michaelmaitland added a comment.

Remove extra space before VLUpperBound.


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Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  string LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  string LLMUL = LargestLMUL.r;
+  int SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+// Cycles for segmented loads and stores are calculated using the
+// formula ceil(2 * nf * lmul).
+class SiFive7GetCyclesSegmented {
+  int c = !cond(
+!eq(mx, "M1") : !mul(!mul(2, nf), 1),
+!eq(mx, "M2") : !mul(!mul(2, nf), 2),
+!eq(mx, "M4") : !mul(!mul(2, nf), 4),
+!eq(mx, "M8") : !mul(!mul(2, nf), 8),
+// We can calculate ceil(a/b) using (a + b - 1) / b.
+// Since the

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf9fa8a599704: [RISCV] Add scheduling information for Zba and 
Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland).

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Files:
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Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -279,11 +308,25 @@
 
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 
//===--===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -279,11 +308,25 @@
 
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 //===--===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
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[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 519921.
michaelmaitland added a comment.

Rebase.


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Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -279,11 +308,25 @@
 
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 
//===--===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -279,11 +308,25 @@
 
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 //===--===//
 // Unsupported extensions
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
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[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

This revision needs to be reopened because it was committed with changes that 
are not relevant to this patch.


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[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

I had to revert this commit because it failed tests that did not fail during 
build through phabricator nor local check-all.


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[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb77d6f51ba4e: [RISCV] Add Scheduling information for Zfh to 
SiFive7 model (authored by michaelmaitland).

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Files:
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Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -110,6 +110,7 @@
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 
@@ -121,6 +122,7 @@
 }
 
 let Latency = 2 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 }
@@ -136,6 +138,22 @@
 def : WriteRes;
 }
 
+// Half precision.
+let Latency = 5 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 14, ResourceCycles = [1, 13] in {
+def :  WriteRes;
+def :  WriteRes;
+}
+
 // Single precision.
 let Latency = 5 in {
 def : WriteRes;
@@ -170,21 +188,33 @@
 
 // Conversions
 let Latency = 3 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
@@ -224,36 +254,55 @@
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 
@@ -446,5 +495,4 @@
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedZfh;
 }
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[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcd02b69e75dd: [RISCV] Add scheduling information for Zba and 
Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland).

Changed prior to commit:
  https://reviews.llvm.org/D149497?vs=518924=519854#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149497/new/

https://reviews.llvm.org/D149497

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -76,6 +76,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -230,11 +259,188 @@
 
 def : ReadAdvance;
 
+// 6. Configuration-Setting Instructions
+def : ReadAdvance;
+def : ReadAdvance;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance;
+def : ReadAdvance;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance;
+def : ReadAdvance;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
+// 12. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 13. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 14. Vector Floating-Point Instructions
+defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" :

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

2023-05-05 Thread Michael Maitland via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG55e196e7718c: [RISCV] Add sifive-x280 processor with all of 
its extensions (authored by michaelmaitland).

Changed prior to commit:
  https://reviews.llvm.org/D149710?vs=518922=519853#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149710/new/

https://reviews.llvm.org/D149710

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Target/RISCV/RISCVProcessors.td


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtV,
+   FeatureStdExtZvl512b,
+   FeatureStdExtZfh,
+   FeatureStdExtZvfh,
+   FeatureStdExtZba,
+   FeatureStdExtZbb],
+  [TuneSiFive7]>;
+
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
   SyntacoreSCR1Model,
   [Feature32Bit,
Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -175,6 +175,7 @@
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
+* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtV,
+   FeatureStdExtZvl512b,
+   FeatureStdExtZfh,
+

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

2023-05-02 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 518925.
michaelmaitland added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149498/new/

https://reviews.llvm.org/D149498

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -239,6 +239,7 @@
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 
@@ -250,6 +251,7 @@
 }
 
 let Latency = 2 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 }
@@ -265,6 +267,22 @@
 def : WriteRes;
 }
 
+// Half precision.
+let Latency = 5 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 14, ResourceCycles = [1, 13] in {
+def :  WriteRes;
+def :  WriteRes;
+}
+
 // Single precision.
 let Latency = 5 in {
 def : WriteRes;
@@ -299,21 +317,33 @@
 
 // Conversions
 let Latency = 3 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
@@ -690,36 +720,55 @@
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 
@@ -911,5 +960,4 @@
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedZfh;
 }
___
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cfe-commits@lists.llvm.org
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[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-05-02 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 518924.
michaelmaitland marked an inline comment as done.
michaelmaitland added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149497/new/

https://reviews.llvm.org/D149497

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -205,6 +205,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -859,10 +888,24 @@
 // Others
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 
//===--===//
 // Unsupported extensions
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -205,6 +205,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -859,10 +888,24 @@
 // Others
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 //===--===//
 // Unsupported extensions
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
___
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[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

2023-05-02 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 518923.
michaelmaitland added a comment.

Split adding sifive-x280 and vector model between this patch and 
https://reviews.llvm.org/D149710


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  string LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  string LLMUL = LargestLMUL.r;
+  int SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+// Cycles for segmented loads and stores are calculated using the
+// formula ceil(2 * nf * lmul).
+class SiFive7GetCyclesSegmented {
+  int c = !cond(
+!eq(mx, "M1") : !mul(!mul(2, nf), 1),
+!eq(mx, "M2") : !mul(!mul(2, nf), 2),
+!eq(mx, "M4") : !mul(!mul(2, nf), 4),
+!eq(mx, "M8") : !mul(!mul(2, nf), 8),
+// We can calculate ceil(a/b) using (a + b - 1) / b.
+//

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

2023-05-02 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland created this revision.
michaelmaitland added reviewers: craig.topper, kito-cheng, reames, pcwang-thead.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, arichardson.
Herald added a project: All.
michaelmaitland requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Add sifive-x280 processor that uses the SiFive7 scheduler model.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149710

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Target/RISCV/RISCVProcessors.td


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtV,
+   FeatureStdExtZvl512b,
+   FeatureStdExtZfh,
+   FeatureStdExtZvfh,
+   FeatureStdExtZba,
+   FeatureStdExtZbb],
+  [TuneSiFive7]>;
+
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
   SyntacoreSCR1Model,
   [Feature32Bit,
Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -171,6 +171,7 @@
 * Updated support experimental vector crypto extensions to version 0.5.1 of
   the specification.
 * Removed N extension (User-Level Interrupts) CSR names in the assembler.
+* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s


Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: clang/test/Driver/riscv-cpus.c:176
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"

craig.topper wrote:
> This means the patch is dependent on the patch that adds sifive-x280?
> This means the patch is dependent on the patch that adds sifive-x280?

Added parent revision.


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[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland marked an inline comment as done.
michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:181
+   FeatureStdExtZvfh,
+   FeatureStdExtZba,
+   FeatureStdExtZbb],

craig.topper wrote:
> This makes the patch dependent on adding sifive-x280
Added parent revision.


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[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 518089.
michaelmaitland added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add zfh to `clang/test/Driver/riscv-cpus.c`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149498/new/

https://reviews.llvm.org/D149498

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -239,6 +239,7 @@
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 
@@ -250,6 +251,7 @@
 }
 
 let Latency = 2 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 }
@@ -265,6 +267,22 @@
 def : WriteRes;
 }
 
+// Half precision.
+let Latency = 5 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 14, ResourceCycles = [1, 13] in {
+def :  WriteRes;
+def :  WriteRes;
+}
+
 // Single precision.
 let Latency = 5 in {
 def : WriteRes;
@@ -299,21 +317,33 @@
 
 // Conversions
 let Latency = 3 in {
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
+def : WriteRes;
+def : WriteRes;
 def : WriteRes;
 def : WriteRes;
 def : WriteRes;
@@ -690,36 +720,55 @@
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 
@@ -911,5 +960,4 @@
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedZfh;
 }
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -173,6 +173,7 @@
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
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[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extenstion in SiFive7

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 518086.
michaelmaitland added a comment.

Remove zfh from x280 check in `clang/test/Driver/riscv-cpus.c`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  string LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  string LLMUL = LargestLMUL.r;
+  int SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+// Cycles for segmented loads and stores are calculated using the
+// formula ceil(2 * nf * lmul).
+class SiFive7GetCyclesSegmented {
+  int c = !cond(
+!eq(mx, "M1") : !mul(!mul(2, nf), 1),
+!eq(mx, "M2") : !mul(!mul(2, nf), 2),
+!eq(mx, "M4") : !mul(!mul(2, nf), 4),
+!eq(mx, "M8") : !mul(!mul(2, nf), 8),
+// We can calculate

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland created this revision.
michaelmaitland added reviewers: craig.topper, kito-cheng, reames.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, arichardson.
Herald added a project: All.
michaelmaitland requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Based on the following description from Andrew W.

- Instructions not mentioned here behave the same as integer ALU ops
- rev8 only executes in the late-A and late-B ALUs
- shNadd[.uw] only execute on the early-B and late-B ALUs
- clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
- pcnt[w] looks exactly like integer multiply

This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Co-Authored-By: topperc 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149497

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -205,6 +205,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def : WriteRes;
+def : WriteRes;
+}
+
 // Memory
 def : WriteRes;
 def : WriteRes;
@@ -859,10 +888,24 @@
 // Others
 def : ReadAdvance;
 
+// Bitmanip
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
 
//===--===//
 // Unsupported extensions
-defm : UnsupportedSchedZba;
-defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -177,7 +177,9 @@
FeatureStdExtV,
FeatureStdExtZvl512b,
FeatureStdExtZfh,
-   FeatureStdExtZvfh],
+   FeatureStdExtZvfh,
+   FeatureStdExtZba,
+   FeatureStdExtZbb],
   [TuneSiFive7]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -174,6 +174,7 @@
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -205,6 +205,35 @@
   let ResourceCycles = [1, 15];
 }
 
+// Bitmanip
+let Latency = 3 in {
+// Rotates are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// clz[w]/ctz[w] are in the late-B ALU.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// cpop[w] look exactly like multiply.
+def : WriteRes;
+def : WriteRes;
+
+// orc.b is in the late-B ALU.
+def : WriteRes;
+
+// rev8 is in the late-A and late-B ALUs.
+def : WriteRes;
+
+// shNadd[.uw] is on the early-B and late-B ALUs.
+def :

[PATCH] D149495: Add sifive-x280 processor and support V extenstion in SiFive7

2023-04-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland created this revision.
michaelmaitland added reviewers: craig.topper, kito-cheng, reames, pcwang-thead.
Herald added subscribers: luke, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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Herald added projects: clang, LLVM.

Add x280 processor that uses SiFive7 with vector extension.


Repository:
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Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

Index: llvm/lib/Target/RISCV/RISCVScheduleV.td
===
--- llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,7 +9,7 @@
 //===--===//
 /// Define scheduler resources associated with def operands.
 
-defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
@@ -38,6 +38,32 @@
 !eq(mx, "MF4"): [16]);
 }
 
+// Helper function to get the largest LMUL from MxList
+// Precondition: MxList is sorted in ascending LMUL order.
+class LargestLMUL MxList> {
+  // MX list is sorted from smallest to largest
+  string r = !foldl(!head(MxList), MxList, last, curr, curr);
+}
+// Helper function to get the smallest SEW that can be used with LMUL mx
+// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet
+class SmallestSEW {
+  int r = !head(!if(isF, SchedSEWSetF.val, SchedSEWSet.val));
+}
+
+// Creates WriteRes for (name, mx, resources) tuple
+multiclass LMULWriteResMX resources,
+  string mx, bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+multiclass LMULSEWWriteResMXSEW resources,
+ string mx, int sew,  bit IsWorstCase> {
+  def : WriteRes(name # "_" # mx # "_E" # sew), resources>;
+  if IsWorstCase then
+def : WriteRes(name # "_WorstCase"), resources>;
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -8,6 +8,131 @@
 
 //===--===//
 
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMX MxList> {
+  string LLMUL = LargestLMUL.r;
+  bit c = !eq(mx, LLMUL);
+}
+
+/// c is true if mx and sew have the worst case behavior compared to LMULs in
+/// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFive7IsWorstCaseMXSEW MxList,
+   bit isF = 0> {
+  string LLMUL = LargestLMUL.r;
+  int SSEW = SmallestSEW.r;
+  bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+class SiFive7GetCyclesDefault {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "M8") : 16,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesWidening {
+  int c = !cond(
+!eq(mx, "M1") : 2,
+!eq(mx, "M2") : 4,
+!eq(mx, "M4") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesNarrowing {
+  int c = !cond(
+!eq(mx, "M1") : 4,
+!eq(mx, "M2") : 8,
+!eq(mx, "M4") : 16,
+!eq(mx, "MF2") : 2,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesOutputLMUL {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 2,
+!eq(mx, "M4") : 4,
+!eq(mx, "M8") : 8,
+!eq(mx, "MF2") : 1,
+!eq(mx, "MF4") : 1,
+!eq(mx, "MF8") : 1
+  );
+}
+
+class SiFive7GetCyclesVMask {
+  int c = !cond(
+!eq(mx, "M1") : 1,
+!eq(mx, "M2") : 1,
+!eq(mx, "M4") : 1,
+!eq(mx, "M8") : 2,
+!eq(mx, "MF2") : 1,
+

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

2023-04-25 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland accepted this revision.
michaelmaitland added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

2023-04-25 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:703
 class VPseudoUSLoadMask :
-  Pseudo<(outs GetVRegNoV0.R:$rd),
-  (ins GetVRegNoV0.R:$merge,
+  Pseudo<(outs GetVRegNoV0'(RetClass):$rd),
+  (ins GetVRegNoV0'(RetClass):$merge,

Typo with the `'`? This also happens multiple times below.




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[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

2023-02-28 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

In D144914#4159291 , @MaskRay wrote:

> Sorry I just saw this but I am not sure this is a good idea. Why can't the 
> user use `--print-supported-cpus` instead? The additional alias doesn't seem 
> useful. If you can make GCC add this as well, it will be different.

According to https://reviews.llvm.org/D63105, I believe the reason `mcpu=?` and 
`mtune=?`  were added was:

> This option is useful but may be hard to discover. Will something like 
> -march=? and -mtune=? make the feature more discoverable?

I would then say this option is being made available for the same reason: 
discoverability. Since `llc` uses `help` instead of `?`, I think that this 
clang option is easier to discover since it exists in other parts of llvm. 
Additionally, it comes with the added benefit that `help` does not contain 
special characters that require escaping. Maybe we revert this patch and remove 
the `?` and only support `help`?

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[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

2023-02-28 Thread Michael Maitland via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG003078b62d8d: [Clang][Driver] Add -mcpu=help and -mtune=help 
to clang (authored by michaelmaitland).

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Files:
  clang/docs/CommandGuide/clang.rst
  clang/include/clang/Driver/Options.td
  clang/test/Driver/print-supported-cpus.c


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 
| \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=help and -mtune=help alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=help -fuse-ld=dummy 
2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_help : Flag<["-"], "mcpu=help">, Alias;
+def mtune_EQ_help : Flag<["-"], "mtune=help">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=help, -mtune=help
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=help and -mtune=help alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=help -fuse-ld=dummy 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_help : Flag<["-"], "mcpu=help">, Alias;
+def mtune_EQ_help : Flag<["-"], "mtune=help">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=help, -mtune=help
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family
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[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

2023-02-27 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland added a comment.

In D144914#4156567 , @reames wrote:

> Code and description appear out of sync.  (help != list)  Personally, I like 
> the help naming a lot better.

Thanks for catching this. I meant to write `help` instead of `list`.


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[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

2023-02-27 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland updated this revision to Diff 500907.
michaelmaitland added a comment.

Change `list` -> `help`.


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Files:
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  clang/include/clang/Driver/Options.td
  clang/test/Driver/print-supported-cpus.c


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 
| \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=help and -mtune=help alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=help -fuse-ld=dummy 
2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_help : Flag<["-"], "mcpu=help">, Alias;
+def mtune_EQ_help : Flag<["-"], "mtune=help">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=help, -mtune=help
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=help and -mtune=help alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=help -fuse-ld=dummy 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_help : Flag<["-"], "mcpu=help">, Alias;
+def mtune_EQ_help : Flag<["-"], "mtune=help">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=help, -mtune=help
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family
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[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

2023-02-27 Thread Michael Maitland via Phabricator via cfe-commits

michaelmaitland created this revision.
michaelmaitland added reviewers: craig.topper, reames.
Herald added a project: All.
michaelmaitland requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Clang currently uses `-mcpu=?`. The `?` causes errors on some shells such as zsh
since it is a special character. In order for it to work on shells such as zsh,
the option must be passed in quotes or escaped. This patch adds `-mcpu=help` as
another alias for `--print-supported-cpus`. In llc, `-mcpu=help` an alias to
print supported cpus.


Repository:
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Files:
  clang/docs/CommandGuide/clang.rst
  clang/include/clang/Driver/Options.td
  clang/test/Driver/print-supported-cpus.c


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 
| \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=list and -mtune=list alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=list 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=list -fuse-ld=dummy 
2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_list : Flag<["-"], "mcpu=list">, Alias;
+def mtune_EQ_list : Flag<["-"], "mtune=list">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=list, -mtune=list
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family


Index: clang/test/Driver/print-supported-cpus.c
===
--- clang/test/Driver/print-supported-cpus.c
+++ clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=list and -mtune=list alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=list 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=list -fuse-ld=dummy 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_list : Flag<["-"], "mcpu=list">, Alias;
+def mtune_EQ_list : Flag<["-"], "mtune=list">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
Index: clang/docs/CommandGuide/clang.rst
===
--- clang/docs/CommandGuide/clang.rst
+++ clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=list, -mtune=list
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family
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