[PATCH] D129855: [clang][PowerPC] Set lld as clang's default linker for PowerPC Linux

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

Hi @MaskRay, could you please take a look at @nemanjai's suggestion?

> ...
> So I would prefer that we handle this in the CMake files if @MaskRay doesn't 
> object.

Thanks!


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[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb6cc5ddc9478: [libLTO] Set data-sections by default in 
libLTO. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll
  llvm/test/LTO/PowerPC/lit.local.cfg

Index: llvm/test/LTO/PowerPC/lit.local.cfg
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+  config.unsupported = True
Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 448036.
quinnp added a comment.

Adding lit config to mark tests as unsupported for non PPC targets.


Repository:
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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll
  llvm/test/LTO/PowerPC/lit.local.cfg

Index: llvm/test/LTO/PowerPC/lit.local.cfg
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+  config.unsupported = True
Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf565444b486d: [libLTO] Set data-sections by default in 
libLTO. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck --check-prefix=CHECK-NOUS %s
+
+
+// RUN: %clang -### %s -flto 2>&1\
+// RUN: 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 448016.
quinnp marked 5 inline comments as done.
quinnp added a comment.

Addressing review comments: fixing test cases and improving test case clarity.


Repository:
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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck --check-prefix=CHECK-NOUS %s
+
+
+// RUN: %clang -### %s -flto 2>&1\
+// RUN: --target=x86_64-unknown-linux \
+// RUN:   | FileCheck 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 447336.
quinnp marked 3 inline comments as done.
quinnp added a comment.

Adressing review comments. Moving tests into `function-sections.c`, using `%s` 
instead of creating a new file with `touch`, and modifying some `CHECK` lines 
to simplify checks.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:  (csect: .data)
+; CHECK:   g O .data {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) {{.*}} var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:579
+  else if (Args.hasArg(options::OPT_fno_data_sections))
+CmdArgs.push_back("-plugin-opt=-data-sections=0");
 

MaskRay wrote:
> Is -plugin-opt=-data-sections=0 a problem for `!UseSeparateSections` targets?
I don't think `-plugin-opt=-data-sections=0` is a problem for 
`!UseSeparateSections` targets because we only add 
`"-plugin-opt=-data-sections=0"` if the user explicitly specified 
`-fno-data-sections`.  
- If `UseSeparateSections` is `true`, we will enter the  `if` block unless 
`-fno-data-sections` is explicitly set.
- If `UseSeparateSections` is `false`, we will enter the `if` block only if  
`-fdata-sections` is explicitly set.

Then, if we did not enter the `if` block, we will only enter the `else if` 
block when `-fno-data-sections` is explicitly set.



Comment at: llvm/test/LTO/PowerPC/data-sections-linux.ll:20
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var

MaskRay wrote:
> What does this `...-NOT: .var` do?
The line `; CHECK-NO-DATA-SECTIONS-NOT: .var` is to ensure that `data-sections` 
is correctly turned off. On Linux, when `data-sections` is on each variable `X` 
will have its own section named `.bss.X`. Here, I am trying to make sure that 
the the `.X` part is not present since it may have been consumed by the 
`{{.*}}` after the check for `.bss` on the next line.


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[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

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quinnp updated this revision to Diff 446597.
quinnp marked 3 inline comments as done.
quinnp added a comment.

Adressed review comments.

- Modified how `llvm-lto` test-cases check the `llvm-objdump -t` output.
- Renamed `gold-lto-sections.c` to `forwarding-sections-liblto.c` and modified 
the test to use the `RUN` lines from `forwarding-sections-liblto.c` with the 
target specified using `--target=`.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:  (csect: .data)
+; CHECK:   g O .data {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) {{.*}} var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,17 @@
+// RUN: touch %t.o
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 | FileCheck %s
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 \
+// RUN:   -ffunction-sections -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-SECTIONS
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 \
+// RUN:   -fno-function-sections -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

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quinnp added a comment.

In D129401#3666238 , @MaskRay wrote:

> Mostly looks good, with a nit in the test and some suggestion to the summary.
>
> In D129401#3662857 , @quinnp wrote:
>
>>> If this is for the legacy LTO interface, please state so.  `lld/*/LTO.cpp` 
>>> sets `c.Options.DataSections = true;` to enable data sections by default.
>>
>> Hey @MaskRay, I'm not sure what is considered the legacy LTO interface, but 
>> this change is to make the `libLTO` codegen match the behaviour of `LTO` 
>> used through `lld` and `gold plugin`. Both `lld` and `gold plugin` turn on 
>> `data-sections` for `LTO` by default:
>>
>> - as you mentioned `lld/*/LTO.cpp` sets `c.Options.DataSections = true;` by 
>> default.
>> - and `llvm/tools/gold/gold-plugin.cpp` sets `Conf.Options.DataSections = 
>> SplitSections;` provided that the user did not explicitly set/unset 
>> `data-sections` where `SplitSections` is `true` unless `gold plugin` is 
>> doing a relocatable link.
>
> There is a legacy LTO interface (see 
> llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h) and a resolution-based 
> interface.
> Change libLTO in "This patch changes libLTO to set data-sections by default." 
> to legacy LTO.
>
>> This patch also fixes the forwarding of the clang options -fno-data-sections 
>> and -fno-function-sections to libLTO
>
> This sentence can keep using libLTO or LLVMLTO (the library is LLVMLTO per 
> llvm/lib/LTO/CMakeLists.txt)

Ah I see, thank you @MaskRay! I've updated the testcases and the summary.


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[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

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quinnp updated this revision to Diff 446228.
quinnp marked an inline comment as done.
quinnp added a comment.

Addressing review comments. Changing test cases to use `llvm-objdump -t` 
instead of `obj2yaml`.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,25 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:  SYMBOL TABLE:
+; CHECK:  .bss.var
+; CHECK-SAME: var
+
+; CHECK-NO-DATA-SECTIONS:  SYMBOL TABLE:
+; CHECK-NO-DATA-SECTIONS:  .bss
+; CHECK-NO-DATA-SECTIONS-NOT:  .var
+; CHECK-NO-DATA-SECTIONS-SAME: var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,25 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  SYMBOL TABLE:
+; CHECK:  .data
+; CHECK-NOT:  (csect: .data)
+; CHECK-SAME: var
+
+; CHECK-NO-DATA-SECTIONS:  SYMBOL TABLE:
+; CHECK-NO-DATA-SECTIONS:  .data (csect: .data)
+; CHECK-NO-DATA-SECTIONS-SAME: var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -4,5 +4,5 @@
 // RUN: -Wl,-plugin-opt=foo -O3 \
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: "-plugin-opt=-function-sections=1"
+// CHECK: "-plugin-opt=-data-sections=1"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,15 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -ffunction-sections -fdata-sections | \
+// RUN:   FileCheck %s --check-prefix=CHECK-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-function-sections -fno-data-sections \
+// RUN:   | FileCheck %s --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: "-plugin-opt=-data-sections=1"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-SECTIONS: "-plugin-opt=-data-sections=1"
+// 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

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quinnp updated this revision to Diff 446147.
quinnp marked 6 inline comments as done.
quinnp added a comment.

Addressing review comments. Fixing the forwarding for -fno-function-sectons and 
removing the ObjectFormatType check.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -4,5 +4,5 @@
 // RUN: -Wl,-plugin-opt=foo -O3 \
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: "-plugin-opt=-function-sections=1"
+// CHECK: "-plugin-opt=-data-sections=1"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,15 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -ffunction-sections -fdata-sections | \
+// RUN:   FileCheck %s --check-prefix=CHECK-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-function-sections -fno-data-sections \
+// RUN:   | FileCheck %s --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445839.
quinnp added a comment.

Modifying a test to fix check lines.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/gold-lto-sections.c
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,11 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections=1"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -5,4 +5,4 @@
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
 // CHECK: "-plugin-opt=-function-sections"
-// CHECK: 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

> If this is for the legacy LTO interface, please state so.  `lld/*/LTO.cpp` 
> sets `c.Options.DataSections = true;` to enable data sections by default.

Hey @MaskRay, I'm not sure what is considered the legacy LTO interface, but 
this change is to make the `libLTO` codegen match the behaviour of `LTO` used 
through `lld` and `gold plugin`. Both `lld` and `gold plugin` turn on 
`data-sections` for `LTO` by default:

- as you mentioned `lld/*/LTO.cpp` sets `c.Options.DataSections = true;` by 
default.
- and `llvm/tools/gold/gold-plugin.cpp` sets `Conf.Options.DataSections = 
SplitSections;` provided that the user did not explicitly set/unset 
`data-sections` where `SplitSections` is `true` unless `gold plugin` is doing a 
relocatable link.

@hubert.reinterpretcast please correct me if I am wrong about why this change 
is needed.




Comment at: llvm/lib/LTO/LTOCodeGenerator.cpp:351
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||

hubert.reinterpretcast wrote:
> w2yehia wrote:
> > quinnp wrote:
> > > w2yehia wrote:
> > > > any reason we do this for ELF and XCOFF only?
> > > I don't think there is a particular reason that we do this for ELF and 
> > > XCOFF only. We needed this fixed for `AIX` (`XCOFF`) and wanted to change 
> > > `Linux` (`ELF`) to match the behaviour of `lld`/`gold` at the same time. 
> > > I'm not sure what other file formats need for this so I did not include 
> > > them.
> > > 
> > > @hubert.reinterpretcast might have a better answer for this.
> > I don't know either about the other formats, was just wondering.
> > I think it's safe to do it for the file formats that we know are currently 
> > different between libLTO and lld/gold. The proposed change is an 
> > improvement with minimal risk.
> I agree with @w2yehia that we should change the data-sections to "on" by 
> default in libLTO for the other file formats where one of lld/the gold plugin 
> sets it to "on".
@hubert.reinterpretcast I think that if we want to change `data-sections` to 
"on" by default for any file format which  `lld` or `gold plugin` set 
data-sections to "on", we would set `data-sections` to "on" for all file 
formats. This is because `gold plugin` does not check the file format when it 
is setting `data-sections`. You can see where `gold plugin` sets 
`data-sections` here: 
https://github.com/llvm/llvm-project/blob/main/llvm/tools/gold/gold-plugin.cpp#L893

Do you suggest that we remove the checks for file format when setting 
`data-sections` in `libLTO`? ie. change the `if` statement to this:
```
if (!codegen::getExplicitDataSections())
  Config.Options.DataSections = true;
```


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[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445835.
quinnp marked an inline comment as done.
quinnp added a comment.

Fixing test case.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/gold-lto-sections.c
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -5,4 +5,4 @@
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
 // CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: 

[PATCH] D129855: [clang][PowerPC] Set lld as clang's default linker for PowerPC Linux

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D129855#3657006 , @MaskRay wrote:

> This is not right as using `ld.lld` as the default linker isn't the majority 
> case. If you want to change the default for your distribution, set 
> `-DCLANG_DEFAULT_LINKER=lld`.
> (Alternatively, you can have a `ld` symlink pointing to `lld`.)

Hi @MaskRay! Do you mean I should abandon this change or find a way to set the 
CMake variable `CLANG_DEFAULT_LINKER` to `lld` as default when building for 
PowerPC Linux? I wasn't able to find any examples of people setting CMake 
variables for specific distributions.

Thanks!


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[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445634.
quinnp added a comment.

Addressing review comment.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -572,9 +572,10 @@
   }
 
   if (Args.hasFlag(options::OPT_fdata_sections, options::OPT_fno_data_sections,
-   UseSeparateSections)) {
-CmdArgs.push_back("-plugin-opt=-data-sections");
-  }
+   UseSeparateSections))
+  

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445631.
quinnp added a comment.

Updating patch to forward `-data-sections=1` to `libLTO`/`gold` instead of just 
`-data-sections` when `-fdata-sections` is explicitly specified in `clang`. 
This is to be more explicit since `-data-sections=0` is now being forwared when 
`-fno-data-sections` is explicitly specified.


Repository:
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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ 

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445628.
quinnp added a comment.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Updating patch with a `clang` change to properly forward `-data-sections=0` to 
`libLTO`/`gold` when `-fno-data-sections` is explicitly specified.


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Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,11 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -576,6 

[PATCH] D129855: [clang][PowerPC] Set lld as clang's default linker for PowerPC Linux

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: steven.zhang, shchenz, kbarton, nemanjai.
Herald added a project: All.
quinnp requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

This patch changes the default linker for `clang` on PowerPC Linux to `lld`.
Here is a summary of the expected behaviour before and after this patch:

To use `lld` as the linker before this patch:

- build with `lld` in `LLVM_ENABLE_PROJECTS`
- build with `-DCLANG_DEFAULT_LINKER=lld`

To use `lld` as the linker after this patch:

- build with `lld` in `LLVM_ENABLE_PROJECTS`

To use `ld` as the linker before this patch:

- default behaviour

To use `ld` as the linker after this patch:

- build with `-DCLANG_DEFAULT_LINKER=`

Note: After this patch, if you build `clang` for PowerPC Linux and `lld` is not
included in `LLVM_ENABLE_PROJECTS`, the built compiler will report an error
during linking on PowerPC Linux. Therefore, anyone using the default behaviour
before this patch will need to modify their build configuration to either:

- include `-DCLANG_DEFAULT_LINKER=` to continue using `ld` or
- `lld` in `LLVM_ENABLE_PROJECTS` to switch to `lld`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129855

Files:
  clang/lib/Driver/ToolChains/PPCLinux.h


Index: clang/lib/Driver/ToolChains/PPCLinux.h
===
--- clang/lib/Driver/ToolChains/PPCLinux.h
+++ clang/lib/Driver/ToolChains/PPCLinux.h
@@ -24,6 +24,8 @@
   AddClangSystemIncludeArgs(const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const override;
 
+  const char *getDefaultLinker() const override { return "ld.lld"; }
+
 private:
   bool SupportIEEEFloat128(const Driver , const llvm::Triple ,
const llvm::opt::ArgList ) const;


Index: clang/lib/Driver/ToolChains/PPCLinux.h
===
--- clang/lib/Driver/ToolChains/PPCLinux.h
+++ clang/lib/Driver/ToolChains/PPCLinux.h
@@ -24,6 +24,8 @@
   AddClangSystemIncludeArgs(const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const override;
 
+  const char *getDefaultLinker() const override { return "ld.lld"; }
+
 private:
   bool SupportIEEEFloat128(const Driver , const llvm::Triple ,
const llvm::opt::ArgList ) const;
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[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

[Quinn Pham via Phabricator via cfe-commits]

quinnp accepted this revision.
quinnp added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


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[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG35aaf548237a: [clang][driver] fix to correctly set 
devtoolset on RHEL (authored by quinnp).

Repository:
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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/unittests/Driver/ToolChainTest.cpp


Index: clang/unittests/Driver/ToolChainTest.cpp
===
--- clang/unittests/Driver/ToolChainTest.cpp
+++ clang/unittests/Driver/ToolChainTest.cpp
@@ -587,9 +587,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/gcc-toolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -603,9 +603,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  
"/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  
"/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Candidate multilib: .;@m64\n"
   "Selected multilib: .;@m64\n",
   S);
@@ -627,9 +627,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/devtoolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -643,9 +643,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/devtoolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/devtoolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Candidate multilib: .;@m64\n"
   "Selected multilib: .;@m64\n",
   S);
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2154,7 +2154,7 @@
 }
 
 if (ChosenToolsetVersion > 0)
-  Prefixes.push_back(ChosenToolsetDir);
+  Prefixes.push_back(ChosenToolsetDir + "/root/usr");
   }
 
   // Fall back to /usr which is used by most non-Solaris systems.


Index: clang/unittests/Driver/ToolChainTest.cpp
===
--- clang/unittests/Driver/ToolChainTest.cpp
+++ clang/unittests/Driver/ToolChainTest.cpp
@@ -587,9 +587,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/gcc-toolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -603,9 +603,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  

[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

Thanks @tbaeder, @MaskRay, and @nemanjai.

> I did not remove that on purpose, so adding it back makes sense to me.

I've updated the patch to remove the path without the `/root/usr` suffix and 
exclusively add the path with the `root/usr` suffix.

> This change also needs a unit test.

I've updated the existing test case to match this change.


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[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 435914.
quinnp added a comment.
Herald added a subscriber: ormris.

Addressing review comments. Removing path without `/root/usr` prefix and 
changing unit test to match.


Repository:
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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/unittests/Driver/ToolChainTest.cpp


Index: clang/unittests/Driver/ToolChainTest.cpp
===
--- clang/unittests/Driver/ToolChainTest.cpp
+++ clang/unittests/Driver/ToolChainTest.cpp
@@ -587,9 +587,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/gcc-toolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -603,9 +603,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  
"/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  
"/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Candidate multilib: .;@m64\n"
   "Selected multilib: .;@m64\n",
   S);
@@ -627,9 +627,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/devtoolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -643,9 +643,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/devtoolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/devtoolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/devtoolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Candidate multilib: .;@m64\n"
   "Selected multilib: .;@m64\n",
   S);
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2154,7 +2154,7 @@
 }
 
 if (ChosenToolsetVersion > 0)
-  Prefixes.push_back(ChosenToolsetDir);
+  Prefixes.push_back(ChosenToolsetDir + "/root/usr");
   }
 
   // Fall back to /usr which is used by most non-Solaris systems.


Index: clang/unittests/Driver/ToolChainTest.cpp
===
--- clang/unittests/Driver/ToolChainTest.cpp
+++ clang/unittests/Driver/ToolChainTest.cpp
@@ -587,9 +587,9 @@
 llvm::MemoryBuffer::getMemBuffer("\n"));
 
 // File needed for GCC installation detection.
-InMemoryFileSystem->addFile(
-"/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11/crtbegin.o", 0,
-llvm::MemoryBuffer::getMemBuffer("\n"));
+InMemoryFileSystem->addFile("/opt/rh/gcc-toolset-12/root/usr/lib/gcc/"
+"x86_64-redhat-linux/11/crtbegin.o",
+0, llvm::MemoryBuffer::getMemBuffer("\n"));
 
 DiagnosticsEngine Diags(DiagID, &*DiagOpts, new SimpleDiagnosticConsumer);
 Driver TheDriver("/bin/clang", "x86_64-redhat-linux", Diags,
@@ -603,9 +603,9 @@
   C->getDefaultToolChain().printVerboseInfo(OS);
 }
 EXPECT_EQ("Found candidate GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  "/opt/rh/gcc-toolset-12/root/usr/lib/gcc/x86_64-redhat-linux/11\n"
   "Selected GCC installation: "
-  "/opt/rh/gcc-toolset-12/lib/gcc/x86_64-redhat-linux/11\n"
+  

[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked 2 inline comments as done.
quinnp added a comment.

Thank you @nemanjai! I've updated the patch based on your suggestion and tested 
it for both the existing testcase and the RHEL buildbot failure.


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[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 435239.
quinnp added a comment.

Addressing review comments.


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2153,8 +2153,10 @@
   }
 }
 
-if (ChosenToolsetVersion > 0)
+if (ChosenToolsetVersion > 0) {
   Prefixes.push_back(ChosenToolsetDir);
+  Prefixes.push_back(ChosenToolsetDir + "/root/usr");
+}
   }
 
   // Fall back to /usr which is used by most non-Solaris systems.


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2153,8 +2153,10 @@
   }
 }
 
-if (ChosenToolsetVersion > 0)
+if (ChosenToolsetVersion > 0) {
   Prefixes.push_back(ChosenToolsetDir);
+  Prefixes.push_back(ChosenToolsetDir + "/root/usr");
+}
   }
 
   // Fall back to /usr which is used by most non-Solaris systems.
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[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added a project: All.
quinnp requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

This patch correctly sets the devtoolset on RHEL.


Repository:
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https://reviews.llvm.org/D127310

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2149,7 +2149,7 @@
 
   if (ToolsetVersion > ChosenToolsetVersion) {
 ChosenToolsetVersion = ToolsetVersion;
-ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str();
+ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str() + "/root/usr";
   }
 }
 


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2149,7 +2149,7 @@
 
   if (ToolsetVersion > ChosenToolsetVersion) {
 ChosenToolsetVersion = ToolsetVersion;
-ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str();
+ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str() + "/root/usr";
   }
 }
 
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[PATCH] D124389: [clang][NFC] Inclusive language: remove use of Whitelist in clang/lib/Analysis/

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0386213352ec: [clang][NFC] Inclusive language: remove use of 
Whitelist in clang/lib/Analysis/ (authored by quinnp).

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Files:
  clang/lib/Analysis/RetainSummaryManager.cpp


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));
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[PATCH] D124389: [clang][NFC] Inclusive language: remove use of Whitelist in clang/lib/Analysis/

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added a project: All.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] As part of using inclusive language within the llvm project, this patch
rewords a comment to replace Whitelist with Allowlist in
`RetainSummaryManager.cpp`.


Repository:
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Files:
  clang/lib/Analysis/RetainSummaryManager.cpp


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));
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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp reopened this revision.
quinnp added a comment.
This revision is now accepted and ready to land.

Re-opening the revision so that I can update it with a fix.


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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D121637#3437371 , @thakis wrote:

> Looks like this breaks tests on windows: 
> http://45.33.8.238/win/55893/step_7.txt
>
> Please take a look and revert for now if it takes a while to fix.

Thanks for finding this, not sure what the cause is. I reverted the commit 
here: https://reviews.llvm.org/rGfef56f79ac8c4a4985774ea9fb1faa83a74866d3.

I'll look into a fix.


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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2aae5b1fac38: [PowerPC] Fix EmitPPCBuiltinExpr to emit 
arguments once (authored by quinnp).

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz();
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421303.
quinnp added a comment.

Fixing a set of builtins added by the rebase with main.


Repository:
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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz();
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 __vector_pair testVPRet1(int *ptr) { // expected-error {{invalid 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421286.
quinnp added a comment.

Rebasing with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz();
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 __vector_pair testVPRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15627
+Value *Y =
+Builder.CreateAnd(EmitScalarExpr(E->getArg(1)), 
Builder.CreateNot(Op3));
 return Builder.CreateOr(X, Y);

nemanjai wrote:
> Nit: I understand that we only have one use of `E->getArg(1)`, but might as 
> well initialize `Op1` as above just for consistency.
I've fixed all the instances of this.


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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421279.
quinnp marked an inline comment as done.
quinnp added a comment.

Fixing some testcases that broke due to re-ordering IR in my last update.


Repository:
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https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz();
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked an inline comment as done.
quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15208
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
-if (E->getArg(i)->getType()->isArrayType())
-  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());

quinnp wrote:
> amyk wrote:
> > A question I have is do we not need to consider 
> > this/`EmitArrayToPointerDecay()` anymore? Was this not used for anything?
> Thanks for your comment! I could not find any builtins that used this case in 
> the loop for emitting their arguments and did not see any failures when I 
> removed it. I am going to look into this now and verify whether or not this 
> is needed.
I've updated the patch to include `EmitArrayToPointerDecay()` where it is 
needed and add code generation testcases to test this functionality.


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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 419126.
quinnp added a comment.

Moving testcases that require code generation from 
`clang/test/Sema/ppc-pair-mma-types.c` to 
`clang/test/CodeGen/PowerPC/ppc-mma-types.c` and 
`clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c`. This is because 
some of these tests use the line 
`Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());` which I 
initially removed from EmitPPCbuiltinExpr. I have added this back in the switch 
statement where it is needed.


Repository:
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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz();
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15208
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
-if (E->getArg(i)->getType()->isArrayType())
-  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());

amyk wrote:
> A question I have is do we not need to consider 
> this/`EmitArrayToPointerDecay()` anymore? Was this not used for anything?
Thanks for your comment! I could not find any builtins that used this case in 
the loop for emitting their arguments and did not see any failures when I 
removed it. I am going to look into this now and verify whether or not this is 
needed.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 416917.
quinnp added a comment.

Fixing a failing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
@@ -95,7 +95,6 @@
 // CHECK-LABEL: @fnmsub(
 // CHECK: [[D_ADDR:%.*]] = alloca double, align 8
 // CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-COUNT-3:load double, double* [[D_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
 // CHECK-NEXT:

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 415412.
quinnp added a comment.

Minor formatting update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
@@ -15,9 +15,8 @@
 
 // CHECK-LABEL: @test_fric(
 // CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @a, align 8
-// CHECK-NEXT:[[TMP2:%.*]] = call double @llvm.rint.f64(double [[TMP1]])
-// CHECK-NEXT:ret double [[TMP2]]
+// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.rint.f64(double [[TMP0]])
+// CHECK-NEXT:ret double 

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Herald added a project: All.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch refactors `EmitPPCBuiltinExpr` in `CGBuiltin.cpp` to remove
the loop at the begining of the function that emits the arguments and
to delay emitting the arguments until inside the switch statement. This
refactor will put `EmitPPCBuiltinExpr` in line with the strategy of the
target independent function `EmitBuiltinExpr`. Also, this refactor
ensures that arguments are only emitted once.

Tests that included builtins affected by the refactor have been modified
to match expected behaviour.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c

[PATCH] D112073: [PowerPC] Emit warning when SP is clobbered by asm

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6a028296fe62: [PowerPC] Emit warning when SP is clobbered by 
asm (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112073/new/

https://reviews.llvm.org/D112073

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Misc/ppc-inline-asm-clobber-warning.c
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll

Index: llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-unknown-unkown \
+; RUN:   -mcpu=pwr7 2>&1 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-unkown \
+; RUN:   -mcpu=pwr7 2>&1 | FileCheck %s
+
+define void @test_r1_clobber() {
+entry:
+  call void asm sideeffect "nop", "~{r1}"()
+  ret void
+}
+
+; CHECK: warning: inline asm clobber list contains reserved registers: R1
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+define void @test_x1_clobber() {
+entry:
+  call void asm sideeffect "nop", "~{x1}"()
+  ret void
+}
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X1
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -91,6 +91,8 @@
   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
 
   BitVector getReservedRegs(const MachineFunction ) const override;
+  bool isAsmClobberable(const MachineFunction ,
+MCRegister PhysReg) const override;
   bool isCallerPreservedPhysReg(MCRegister PhysReg,
 const MachineFunction ) const override;
 
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -390,6 +390,18 @@
   return Reserved;
 }
 
+bool PPCRegisterInfo::isAsmClobberable(const MachineFunction ,
+   MCRegister PhysReg) const {
+  // We cannot use getReservedRegs() to find the registers that are not asm
+  // clobberable because there are some reserved registers which can be
+  // clobbered by inline asm. For example, when LR is clobbered, the register is
+  // saved and restored. We will hardcode the registers that are not asm
+  // cloberable in this function.
+
+  // The stack pointer (R1/X1) is not clobberable by inline asm
+  return PhysReg != PPC::R1 && PhysReg != PPC::X1;
+}
+
 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction ) const {
   const PPCSubtarget  = MF.getSubtarget();
   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
Index: clang/test/Misc/ppc-inline-asm-clobber-warning.c
===
--- /dev/null
+++ clang/test/Misc/ppc-inline-asm-clobber-warning.c
@@ -0,0 +1,38 @@
+/// This test checks that the warning includes the location in the C source
+/// file that contains the inline asm. Although this warning is emitted in llvm
+/// it cannot be tested from IR as it does not have that location information at
+/// that stage.
+
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang --target=powerpc-unknown-unknown -mcpu=pwr7 \
+// RUN:   -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang --target=powerpc64-unknown-unknown -mcpu=pwr7 \
+// RUN:   -c %s -o /dev/null 2>&1 | FileCheck %s
+
+void test_r1_clobber() {
+  __asm__("nop":::"r1");
+}
+
+// CHECK:  ppc-inline-asm-clobber-warning.c:14:11: warning: inline asm clobber list contains reserved registers: R1 [-Winline-asm]
+// CHECK-NEXT:   __asm__("nop":::"r1");
+// CHECK-NEXT:   ^
+// CHECK-NEXT: ppc-inline-asm-clobber-warning.c:14:11: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+void test_1_clobber() {
+  __asm__("nop":::"1");
+}
+
+// CHECK:  ppc-inline-asm-clobber-warning.c:23:11: warning: inline asm clobber list contains reserved registers: R1 [-Winline-asm]
+// CHECK-NEXT:   __asm__("nop":::"1");
+// CHECK-NEXT:   ^
+// CHECK-NEXT: ppc-inline-asm-clobber-warning.c:23:11: note: Reserved registers on the clobber list may not be preserved across the 

[PATCH] D112073: [PowerPC] Emit warning when SP is clobbered by asm

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 395687.
quinnp added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Adressing review comments. Added register alias "sp" for the register "r1".
Added a front end testcase to test the location information and all of the
aliases for "r1". Merged the back end test cases so that we are testing both
"r1" and "x1" in 32bit and 64bit.


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Misc/ppc-inline-asm-clobber-warning.c
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll

Index: llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-unknown-unkown \
+; RUN:   -mcpu=pwr7 2>&1 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-unkown \
+; RUN:   -mcpu=pwr7 2>&1 | FileCheck %s
+
+define void @test_r1_clobber() {
+entry:
+  call void asm sideeffect "nop", "~{r1}"()
+  ret void
+}
+
+; CHECK: warning: inline asm clobber list contains reserved registers: R1
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+define void @test_x1_clobber() {
+entry:
+  call void asm sideeffect "nop", "~{x1}"()
+  ret void
+}
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X1
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -91,6 +91,8 @@
   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
 
   BitVector getReservedRegs(const MachineFunction ) const override;
+  bool isAsmClobberable(const MachineFunction ,
+MCRegister PhysReg) const override;
   bool isCallerPreservedPhysReg(MCRegister PhysReg,
 const MachineFunction ) const override;
 
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -390,6 +390,18 @@
   return Reserved;
 }
 
+bool PPCRegisterInfo::isAsmClobberable(const MachineFunction ,
+   MCRegister PhysReg) const {
+  // We cannot use getReservedRegs() to find the registers that are not asm
+  // clobberable because there are some reserved registers which can be
+  // clobbered by inline asm. For example, when LR is clobbered, the register is
+  // saved and restored. We will hardcode the registers that are not asm
+  // cloberable in this function.
+
+  // The stack pointer (R1/X1) is not clobberable by inline asm
+  return PhysReg != PPC::R1 && PhysReg != PPC::X1;
+}
+
 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction ) const {
   const PPCSubtarget  = MF.getSubtarget();
   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
Index: clang/test/Misc/ppc-inline-asm-clobber-warning.c
===
--- /dev/null
+++ clang/test/Misc/ppc-inline-asm-clobber-warning.c
@@ -0,0 +1,38 @@
+/// This test checks that the warning includes the location in the C source
+/// file that contains the inline asm. Although this warning is emitted in llvm
+/// it cannot be tested from IR as it does not have that location information at
+/// that stage.
+
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang --target=powerpc-unknown-unknown -mcpu=pwr7 \
+// RUN:   -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang --target=powerpc64-unknown-unknown -mcpu=pwr7 \
+// RUN:   -c %s -o /dev/null 2>&1 | FileCheck %s
+
+void test_r1_clobber() {
+  __asm__("nop":::"r1");
+}
+
+// CHECK:  ppc-inline-asm-clobber-warning.c:14:11: warning: inline asm clobber list contains reserved registers: R1 [-Winline-asm]
+// CHECK-NEXT:   __asm__("nop":::"r1");
+// CHECK-NEXT:   ^
+// CHECK-NEXT: ppc-inline-asm-clobber-warning.c:14:11: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+void test_1_clobber() {
+  __asm__("nop":::"1");
+}
+
+// CHECK:  ppc-inline-asm-clobber-warning.c:23:11: warning: inline asm clobber list contains reserved registers: R1 [-Winline-asm]
+// CHECK-NEXT:   

[PATCH] D114090: [NFC] Inclusive language: rename master flag to main flag

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb11c66accfb1: [NFC] Inclusive language: rename master flag 
to main flag (authored by quinnp).

Repository:
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Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp


Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -148,7 +148,7 @@
   AlignBranchType.addKind(X86::AlignBranchJcc);
   AlignBranchType.addKind(X86::AlignBranchJmp);
 }
-// Allow overriding defaults set by master flag
+// Allow overriding defaults set by main flag
 if (X86AlignBranchBoundary.getNumOccurrences())
   AlignBoundary = assumeAligned(X86AlignBranchBoundary);
 if (X86AlignBranch.getNumOccurrences())
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -403,7 +403,7 @@
 }
 
 /// Adds exception related arguments to the driver command arguments. There's a
-/// master flag, -fexceptions and also language specific flags to 
enable/disable
+/// main flag, -fexceptions and also language specific flags to enable/disable
 /// C++ and Objective-C exceptions. This makes it possible to for example
 /// disable C++ exceptions but enable Objective-C exceptions.
 static bool addExceptionArgs(const ArgList , types::ID InputType,


Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -148,7 +148,7 @@
   AlignBranchType.addKind(X86::AlignBranchJcc);
   AlignBranchType.addKind(X86::AlignBranchJmp);
 }
-// Allow overriding defaults set by master flag
+// Allow overriding defaults set by main flag
 if (X86AlignBranchBoundary.getNumOccurrences())
   AlignBoundary = assumeAligned(X86AlignBranchBoundary);
 if (X86AlignBranch.getNumOccurrences())
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -403,7 +403,7 @@
 }
 
 /// Adds exception related arguments to the driver command arguments. There's a
-/// master flag, -fexceptions and also language specific flags to enable/disable
+/// main flag, -fexceptions and also language specific flags to enable/disable
 /// C++ and Objective-C exceptions. This makes it possible to for example
 /// disable C++ exceptions but enable Objective-C exceptions.
 static bool addExceptionArgs(const ArgList , types::ID InputType,
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[PATCH] D114029: [clang][NFC] Inclusive terms: rename AccessDeclContextSanity to AccessDeclContextCheck

[Quinn Pham via Phabricator via cfe-commits]

quinnp accepted this revision.
quinnp added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D114100: [NFC][clang-tools-extra] Inclusive language: replace master with main

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc3dc6b081da6: [NFC][clang-tools-extra] Inclusive language: 
replace master with main (authored by quinnp).

Repository:
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Files:
  clang-tools-extra/test/modularize/SubModule2.h


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"
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[PATCH] D114100: [NFC][clang-tools-extra] Inclusive language: replace master with main

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

@sammccall could you take a look at the other changes when you have time? 
Thanks!


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[PATCH] D114108: [NFC][clang] Inclusive language: rename master variable to controller in debug-info tests

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGad501054f1b5: [NFC][clang] Inclusive language: rename master 
variable to controller in debug… (authored by quinnp).

Repository:
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Files:
  clang/test/CodeGenObjC/debug-info-block-helper.m
  cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m


Index: cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
===
--- cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
+++ cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
@@ -11,7 +11,7 @@
 // CHECK: ${{[0-9]}} = 1
 // DEBUGGER: p dbTransaction
 // CHECK: ${{[0-9]}} = 0
-// DEBUGGER: p master
+// DEBUGGER: p controller
 // CHECK: ${{[0-9]}} = 0
 
 #include 
@@ -21,16 +21,16 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-   (void) master; 
+   (void) controller; 
(void) dbTransaction; 
m2++;
return m2;
};
-  master = x();
+  controller = x();
 }
 @end
 
Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-   (void) master; 
+   (void) controller; 
(void) dbTransaction; 
m2++;
return m2;
 
};
-  master = x();
+  controller = x();
 }
 @end
 


Index: cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
===
--- cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
+++ cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
@@ -11,7 +11,7 @@
 // CHECK: ${{[0-9]}} = 1
 // DEBUGGER: p dbTransaction
 // CHECK: ${{[0-9]}} = 0
-// DEBUGGER: p master
+// DEBUGGER: p controller
 // CHECK: ${{[0-9]}} = 0
 
 #include 
@@ -21,16 +21,16 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-	(void) master; 
+	(void) controller; 
 	(void) dbTransaction; 
 	m2++;
 	return m2;
 	};
-  master = x();
+  controller = x();
 }
 @end
 
Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-	(void) master; 
+	(void) controller; 
 	(void) dbTransaction; 
 	m2++;
 	return m2;
 
 	};
-  master = x();
+  controller = x();
 }
 @end
 
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[PATCH] D114108: [NFC][clang] Inclusive language: rename master variable to controller in debug-info-block-helper.m

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 388511.
quinnp added a comment.

Changing master to controller in another testcase.


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Files:
  clang/test/CodeGenObjC/debug-info-block-helper.m
  cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m


Index: cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
===
--- cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
+++ cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
@@ -11,7 +11,7 @@
 // CHECK: ${{[0-9]}} = 1
 // DEBUGGER: p dbTransaction
 // CHECK: ${{[0-9]}} = 0
-// DEBUGGER: p master
+// DEBUGGER: p controller
 // CHECK: ${{[0-9]}} = 0
 
 #include 
@@ -21,16 +21,16 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-   (void) master; 
+   (void) controller; 
(void) dbTransaction; 
m2++;
return m2;
};
-  master = x();
+  controller = x();
 }
 @end
 
Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-   (void) master; 
+   (void) controller; 
(void) dbTransaction; 
m2++;
return m2;
 
};
-  master = x();
+  controller = x();
 }
 @end
 


Index: cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
===
--- cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
+++ cross-project-tests/debuginfo-tests/llgdb-tests/blocks.m
@@ -11,7 +11,7 @@
 // CHECK: ${{[0-9]}} = 1
 // DEBUGGER: p dbTransaction
 // CHECK: ${{[0-9]}} = 0
-// DEBUGGER: p master
+// DEBUGGER: p controller
 // CHECK: ${{[0-9]}} = 0
 
 #include 
@@ -21,16 +21,16 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-	(void) master; 
+	(void) controller; 
 	(void) dbTransaction; 
 	m2++;
 	return m2;
 	};
-  master = x();
+  controller = x();
 }
 @end
 
Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-	(void) master; 
+	(void) controller; 
 	(void) dbTransaction; 
 	m2++;
 	return m2;
 
 	};
-  master = x();
+  controller = x();
 }
 @end
 
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[PATCH] D113505: [NFC][clang] Inclusive language: replace masterPort with mainPort

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7a14244cc645: [NFC][clang] Inclusive language: replace 
masterPort with mainPort (authored by quinnp).

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Files:
  clang/test/ARCMT/objcmt-arc-cf-annotations.m
  clang/test/ARCMT/objcmt-arc-cf-annotations.m.result
  clang/test/Analysis/Inputs/expected-plists/retain-release.m.objc.plist
  clang/test/Analysis/Inputs/expected-plists/retain-release.m.objcpp.plist
  clang/test/Analysis/retain-release-inline.m
  clang/test/Analysis/retain-release.m
  clang/test/Analysis/retain-release.mm

Index: clang/test/Analysis/retain-release.mm
===
--- clang/test/Analysis/retain-release.mm
+++ clang/test/Analysis/retain-release.mm
@@ -175,14 +175,14 @@
 typedef io_object_t io_service_t;
 typedef struct IONotificationPort * IONotificationPortRef;
 typedef void (*IOServiceMatchingCallback)(  void * refcon,  io_iterator_t iterator );
-io_service_t IOServiceGetMatchingService(  mach_port_t masterPort,  CFDictionaryRef matching );
-kern_return_t IOServiceGetMatchingServices(  mach_port_t masterPort,  CFDictionaryRef matching,  io_iterator_t * existing );
-kern_return_t IOServiceAddNotification(  mach_port_t masterPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated));
+io_service_t IOServiceGetMatchingService(  mach_port_t mainPort,  CFDictionaryRef matching );
+kern_return_t IOServiceGetMatchingServices(  mach_port_t mainPort,  CFDictionaryRef matching,  io_iterator_t * existing );
+kern_return_t IOServiceAddNotification(  mach_port_t mainPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated));
 kern_return_t IOServiceAddMatchingNotification(  IONotificationPortRef notifyPort,  const io_name_t notificationType,  CFDictionaryRef matching, IOServiceMatchingCallback callback, void * refCon,  io_iterator_t * notification );
 CFMutableDictionaryRef IOServiceMatching(  const char * name );
 CFMutableDictionaryRef IOServiceNameMatching(  const char * name );
-CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t masterPort,  uint32_t options,  const char * bsdName );
-CFMutableDictionaryRef IOOpenFirmwarePathMatching(  mach_port_t masterPort,  uint32_t options,  const char * path );
+CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t mainPort,  uint32_t options,  const char * bsdName );
+CFMutableDictionaryRef IOOpenFirmwarePathMatching(  mach_port_t mainPort,  uint32_t options,  const char * path );
 CFMutableDictionaryRef IORegistryEntryIDMatching(  uint64_t entryID );
 typedef struct __DASession * DASessionRef;
 extern DASessionRef DASessionCreate( CFAllocatorRef allocator );
Index: clang/test/Analysis/retain-release.m
===
--- clang/test/Analysis/retain-release.m
+++ clang/test/Analysis/retain-release.m
@@ -233,14 +233,14 @@
 typedef io_object_t io_service_t;
 typedef struct IONotificationPort * IONotificationPortRef;
 typedef void (*IOServiceMatchingCallback)(  void * refcon,  io_iterator_t iterator );
-io_service_t IOServiceGetMatchingService(  mach_port_t masterPort,  CFDictionaryRef matching );
-kern_return_t IOServiceGetMatchingServices(  mach_port_t masterPort,  CFDictionaryRef matching,  io_iterator_t * existing );
-kern_return_t IOServiceAddNotification(  mach_port_t masterPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated)); // expected-note {{'IOServiceAddNotification' has been explicitly marked deprecated here}}
+io_service_t IOServiceGetMatchingService(  mach_port_t mainPort,  CFDictionaryRef matching );
+kern_return_t IOServiceGetMatchingServices(  mach_port_t mainPort,  CFDictionaryRef matching,  io_iterator_t * existing );
+kern_return_t IOServiceAddNotification(  mach_port_t mainPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated)); // expected-note {{'IOServiceAddNotification' has been explicitly marked deprecated here}}
 kern_return_t IOServiceAddMatchingNotification(  IONotificationPortRef notifyPort,  const io_name_t notificationType,  CFDictionaryRef matching, IOServiceMatchingCallback callback, void * refCon,  io_iterator_t * notification );
 CFMutableDictionaryRef IOServiceMatching(  const char * name );
 CFMutableDictionaryRef IOServiceNameMatching(  const char * name );
-CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t masterPort,  uint32_t 

[PATCH] D114100: [NFC][clang-tools-extra] Inclusive language: replace master with main

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 387990.
quinnp marked an inline comment as done.
quinnp added a comment.

Addressing review comments. Reverting change to `Protocol.h`.


Repository:
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Files:
  clang-tools-extra/test/modularize/SubModule2.h


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"
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[PATCH] D114100: [NFC][clang-tools-extra] Inclusive language: replace master with main

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked an inline comment as done.
quinnp added inline comments.



Comment at: clang-tools-extra/clangd/Protocol.h:141
   /// the server can send `null` to indicate that the version is known and the
-  /// content on disk is the master (as speced with document content 
ownership).
+  /// content on disk is the main (as speced with document content ownership).
   ///

sammccall wrote:
> This is quoting 
> https://microsoft.github.io/language-server-protocol/specification.
> I think they accept PRs though.
Thanks @sammccall, I'll remove this change from the patch.


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[PATCH] D114108: [NFC][clang] Inclusive language: rename master variable to controller in debug-info-block-helper.m

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] As part of using inclusive language within the llvm project, this patch
replaces master with controller in `debug-info-block-helper.m`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114108

Files:
  clang/test/CodeGenObjC/debug-info-block-helper.m


Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-   (void) master; 
+   (void) controller; 
(void) dbTransaction; 
m2++;
return m2;
 
};
-  master = x();
+  controller = x();
 }
 @end
 


Index: clang/test/CodeGenObjC/debug-info-block-helper.m
===
--- clang/test/CodeGenObjC/debug-info-block-helper.m
+++ clang/test/CodeGenObjC/debug-info-block-helper.m
@@ -12,17 +12,17 @@
 @interface A:NSObject @end
 @implementation A
 - (void) helper {
- int master = 0;
+ int controller = 0;
  __block int m2 = 0;
  __block int dbTransaction = 0;
  int (^x)(void) = ^(void) { (void) self; 
-	(void) master; 
+	(void) controller; 
 	(void) dbTransaction; 
 	m2++;
 	return m2;
 
 	};
-  master = x();
+  controller = x();
 }
 @end
 
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[PATCH] D114100: [NFC][clang-tools-extra] Inclusive language: replace master with main

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: usaxena95, kadircet, arphaman.
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Herald added a project: clang-tools-extra.
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[NFC] As part of using inclusive language within the llvm project, this patch
replaces master with main in these comments.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114100

Files:
  clang-tools-extra/clangd/Protocol.h
  clang-tools-extra/test/modularize/SubModule2.h


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"
Index: clang-tools-extra/clangd/Protocol.h
===
--- clang-tools-extra/clangd/Protocol.h
+++ clang-tools-extra/clangd/Protocol.h
@@ -138,7 +138,7 @@
   /// identifier is sent from the server to the client and the file is not open
   /// in the editor (the server has not received an open notification before)
   /// the server can send `null` to indicate that the version is known and the
-  /// content on disk is the master (as speced with document content 
ownership).
+  /// content on disk is the main (as speced with document content ownership).
   ///
   /// The version number of a document will increase after each change,
   /// including undo/redo. The number doesn't need to be consecutive.


Index: clang-tools-extra/test/modularize/SubModule2.h
===
--- clang-tools-extra/test/modularize/SubModule2.h
+++ clang-tools-extra/test/modularize/SubModule2.h
@@ -1,3 +1,3 @@
-// SubModule2.h - Master header with same name as directory.
+// SubModule2.h - Main header with same name as directory.
 #include "SubModule2/Header3.h"
 #include "SubModule2/Header4.h"
Index: clang-tools-extra/clangd/Protocol.h
===
--- clang-tools-extra/clangd/Protocol.h
+++ clang-tools-extra/clangd/Protocol.h
@@ -138,7 +138,7 @@
   /// identifier is sent from the server to the client and the file is not open
   /// in the editor (the server has not received an open notification before)
   /// the server can send `null` to indicate that the version is known and the
-  /// content on disk is the master (as speced with document content ownership).
+  /// content on disk is the main (as speced with document content ownership).
   ///
   /// The version number of a document will increase after each change,
   /// including undo/redo. The number doesn't need to be consecutive.
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[PATCH] D114090: [NFC] Inclusive language: rename master flag to main flag

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: pengfei, hiraditya.
quinnp requested review of this revision.
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[NFC] As part of using inclusive language within the llvm project, this patch
renames master flag to main flag in these comments.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114090

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp


Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -148,7 +148,7 @@
   AlignBranchType.addKind(X86::AlignBranchJcc);
   AlignBranchType.addKind(X86::AlignBranchJmp);
 }
-// Allow overriding defaults set by master flag
+// Allow overriding defaults set by main flag
 if (X86AlignBranchBoundary.getNumOccurrences())
   AlignBoundary = assumeAligned(X86AlignBranchBoundary);
 if (X86AlignBranch.getNumOccurrences())
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -403,7 +403,7 @@
 }
 
 /// Adds exception related arguments to the driver command arguments. There's a
-/// master flag, -fexceptions and also language specific flags to 
enable/disable
+/// main flag, -fexceptions and also language specific flags to enable/disable
 /// C++ and Objective-C exceptions. This makes it possible to for example
 /// disable C++ exceptions but enable Objective-C exceptions.
 static bool addExceptionArgs(const ArgList , types::ID InputType,


Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -148,7 +148,7 @@
   AlignBranchType.addKind(X86::AlignBranchJcc);
   AlignBranchType.addKind(X86::AlignBranchJmp);
 }
-// Allow overriding defaults set by master flag
+// Allow overriding defaults set by main flag
 if (X86AlignBranchBoundary.getNumOccurrences())
   AlignBoundary = assumeAligned(X86AlignBranchBoundary);
 if (X86AlignBranch.getNumOccurrences())
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -403,7 +403,7 @@
 }
 
 /// Adds exception related arguments to the driver command arguments. There's a
-/// master flag, -fexceptions and also language specific flags to enable/disable
+/// main flag, -fexceptions and also language specific flags to enable/disable
 /// C++ and Objective-C exceptions. This makes it possible to for example
 /// disable C++ exceptions but enable Objective-C exceptions.
 static bool addExceptionArgs(const ArgList , types::ID InputType,
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[PATCH] D113433: [NFC][clang] Inclusive language: Rename myMaster in testcase

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5ed404a4abd3: [NFC][clang] Inclusive language: Rename 
myMaster in testcase (authored by quinnp).

Repository:
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Files:
  clang/test/Rewriter/line-generation-test.m
  clang/test/SemaObjC/warn-direct-ivar-access.m


Index: clang/test/SemaObjC/warn-direct-ivar-access.m
===
--- clang/test/SemaObjC/warn-direct-ivar-access.m
+++ clang/test/SemaObjC/warn-direct-ivar-access.m
@@ -3,39 +3,39 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink; // expected-error {{existing instance variable 
'_isTickledPink' for property 'isTickledPink'}}
 int _myIntProp;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink; // expected-note {{property declared here}}
 @property int myIntProp;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink; // expected-note {{property 
synthesized here}}
 @synthesize myIntProp = _myIntProp;
 
 - (void) doSomething {
-_myMaster = _isTickledPink; // expected-warning {{instance variable 
'_myMaster' is being directly accessed}} \
+_myLeader = _isTickledPink; // expected-warning {{instance variable 
'_myLeader' is being directly accessed}} \
 // expected-warning {{instance variable '_isTickledPink' is being directly 
accessed}}
 }
 
 - (id) init {
-_myMaster=0;
-return _myMaster;
+_myLeader=0;
+return _myLeader;
 }
-- (void) dealloc { _myMaster = 0; }
+- (void) dealloc { _myLeader = 0; }
 @end
 
 MyObject * foo ()
 {
MyObject* p=0;
-p.isTickledPink = p.myMaster;  // ok
-   p->_isTickledPink = (*p)._myMaster; // expected-warning {{instance 
variable '_isTickledPink' is being directly accessed}} \
-// expected-warning {{instance variable '_myMaster' is being directly 
accessed}}
+p.isTickledPink = p.myLeader;  // ok
+   p->_isTickledPink = (*p)._myLeader; // expected-warning {{instance 
variable '_isTickledPink' is being directly accessed}} \
+// expected-warning {{instance variable '_myLeader' is being directly 
accessed}}
 if (p->_myIntProp) // expected-warning {{instance variable 
'_myIntProp' is being directly accessed}}
   p->_myIntProp = 0; // expected-warning {{instance variable 
'_myIntProp' is being directly accessed}}
return p->_isTickledPink; // expected-warning {{instance variable 
'_isTickledPink' is being directly accessed}}
Index: clang/test/Rewriter/line-generation-test.m
===
--- clang/test/Rewriter/line-generation-test.m
+++ clang/test/Rewriter/line-generation-test.m
@@ -7,20 +7,20 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink;
 
 - (void) doSomething {
-_myMaster = _isTickledPink;
+_myLeader = _isTickledPink;
 }
 
 @end
@@ -28,8 +28,8 @@
 MyObject * foo ()
 {
MyObject* p;
-p.isTickledPink = p.myMaster;  // ok
-   p->_isTickledPink = p->_myMaster;
+p.isTickledPink = p.myLeader;  // ok
+   p->_isTickledPink = p->_myLeader;
return p->_isTickledPink;
 }
 


Index: clang/test/SemaObjC/warn-direct-ivar-access.m
===
--- clang/test/SemaObjC/warn-direct-ivar-access.m
+++ clang/test/SemaObjC/warn-direct-ivar-access.m
@@ -3,39 +3,39 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink; // expected-error {{existing instance variable '_isTickledPink' for property 'isTickledPink'}}
 int _myIntProp;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink; // expected-note {{property declared here}}
 @property int myIntProp;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink; // expected-note {{property synthesized here}}
 @synthesize myIntProp = _myIntProp;
 
 - (void) doSomething {
-_myMaster = _isTickledPink; // expected-warning {{instance variable '_myMaster' is being directly accessed}} \
+_myLeader = _isTickledPink; // expected-warning {{instance variable '_myLeader' is being directly accessed}} 

[PATCH] D113942: [NFC][clang] Inclusive language: replace master with main in convert_arm_neon.py

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd4b28a0fe685: [NFC][clang] Inclusive language: replace 
master with main in convert_arm_neon.py (authored by quinnp).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/utils/convert_arm_neon.py


Index: clang/utils/convert_arm_neon.py
===
--- clang/utils/convert_arm_neon.py
+++ clang/utils/convert_arm_neon.py
@@ -7,7 +7,7 @@
 # using the old single-char type modifiers to an equivalent new-style form 
where
 # each modifier is orthogonal and they can be composed.
 #
-# It was used to directly generate the .td files on master, so if you have any
+# It was used to directly generate the .td files on main, so if you have any
 # local additions I would suggest implementing any modifiers here, and running
 # it over your entire pre-merge .td files rather than trying to resolve any
 # conflicts manually.


Index: clang/utils/convert_arm_neon.py
===
--- clang/utils/convert_arm_neon.py
+++ clang/utils/convert_arm_neon.py
@@ -7,7 +7,7 @@
 # using the old single-char type modifiers to an equivalent new-style form where
 # each modifier is orthogonal and they can be composed.
 #
-# It was used to directly generate the .td files on master, so if you have any
+# It was used to directly generate the .td files on main, so if you have any
 # local additions I would suggest implementing any modifiers here, and running
 # it over your entire pre-merge .td files rather than trying to resolve any
 # conflicts manually.
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[PATCH] D113942: [NFC] Inclusive language: replace master with main in convert_arm_neon.py

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added a subscriber: kristof.beyls.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] As part of using inclusive language within the llvm project and to
match the renamed master branch, this patch replaces master with main in
`convert_arm_neon.py`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113942

Files:
  clang/utils/convert_arm_neon.py


Index: clang/utils/convert_arm_neon.py
===
--- clang/utils/convert_arm_neon.py
+++ clang/utils/convert_arm_neon.py
@@ -7,7 +7,7 @@
 # using the old single-char type modifiers to an equivalent new-style form 
where
 # each modifier is orthogonal and they can be composed.
 #
-# It was used to directly generate the .td files on master, so if you have any
+# It was used to directly generate the .td files on main, so if you have any
 # local additions I would suggest implementing any modifiers here, and running
 # it over your entire pre-merge .td files rather than trying to resolve any
 # conflicts manually.


Index: clang/utils/convert_arm_neon.py
===
--- clang/utils/convert_arm_neon.py
+++ clang/utils/convert_arm_neon.py
@@ -7,7 +7,7 @@
 # using the old single-char type modifiers to an equivalent new-style form where
 # each modifier is orthogonal and they can be composed.
 #
-# It was used to directly generate the .td files on master, so if you have any
+# It was used to directly generate the .td files on main, so if you have any
 # local additions I would suggest implementing any modifiers here, and running
 # it over your entire pre-merge .td files rather than trying to resolve any
 # conflicts manually.
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[PATCH] D113299: [NFC] Inclusive Language: change master to main for .chm files

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc3b15b71ce00: [NFC] Inclusive Language: change master to 
main for .chm files (authored by quinnp).

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113299/new/

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Files:
  clang-tools-extra/docs/doxygen.cfg.in
  clang/docs/doxygen.cfg.in
  flang/docs/doxygen.cfg.in
  lldb/docs/doxygen.cfg.in
  llvm/docs/doxygen.cfg.in
  mlir/docs/doxygen.cfg.in
  openmp/docs/doxygen.cfg.in
  openmp/runtime/doc/doxygen/config
  polly/docs/doxygen.cfg.in

Index: polly/docs/doxygen.cfg.in
===
--- polly/docs/doxygen.cfg.in
+++ polly/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: openmp/runtime/doc/doxygen/config
===
--- openmp/runtime/doc/doxygen/config
+++ openmp/runtime/doc/doxygen/config
@@ -1048,7 +1048,7 @@
 
 # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
 # controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
+# it should be included in the main .chm file (NO).
 
 GENERATE_CHI   = NO
 
Index: openmp/docs/doxygen.cfg.in
===
--- openmp/docs/doxygen.cfg.in
+++ openmp/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: mlir/docs/doxygen.cfg.in
===
--- mlir/docs/doxygen.cfg.in
+++ mlir/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: llvm/docs/doxygen.cfg.in
===
--- llvm/docs/doxygen.cfg.in
+++ llvm/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: lldb/docs/doxygen.cfg.in
===
--- lldb/docs/doxygen.cfg.in
+++ lldb/docs/doxygen.cfg.in
@@ -916,7 +916,7 @@
 
 # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
 # controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
+# it should be included in the main .chm file (NO).
 
 GENERATE_CHI   = NO
 
Index: flang/docs/doxygen.cfg.in
===
--- flang/docs/doxygen.cfg.in
+++ flang/docs/doxygen.cfg.in
@@ -1222,7 +1222,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: clang/docs/doxygen.cfg.in
===
--- clang/docs/doxygen.cfg.in
+++ clang/docs/doxygen.cfg.in
@@ -1219,7 +1219,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: clang-tools-extra/docs/doxygen.cfg.in
===
--- clang-tools-extra/docs/doxygen.cfg.in
+++ clang-tools-extra/docs/doxygen.cfg.in
@@ -1230,7 +1230,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate 

[PATCH] D113505: [NFC] Inclusive language: replace masterPort with mainPort

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] This patch replaces `masterPort` with `mainPort` in these
testcases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113505

Files:
  clang/test/ARCMT/objcmt-arc-cf-annotations.m
  clang/test/ARCMT/objcmt-arc-cf-annotations.m.result
  clang/test/Analysis/Inputs/expected-plists/retain-release.m.objc.plist
  clang/test/Analysis/Inputs/expected-plists/retain-release.m.objcpp.plist
  clang/test/Analysis/retain-release-inline.m
  clang/test/Analysis/retain-release.m
  clang/test/Analysis/retain-release.mm

Index: clang/test/Analysis/retain-release.mm
===
--- clang/test/Analysis/retain-release.mm
+++ clang/test/Analysis/retain-release.mm
@@ -175,14 +175,14 @@
 typedef io_object_t io_service_t;
 typedef struct IONotificationPort * IONotificationPortRef;
 typedef void (*IOServiceMatchingCallback)(  void * refcon,  io_iterator_t iterator );
-io_service_t IOServiceGetMatchingService(  mach_port_t masterPort,  CFDictionaryRef matching );
-kern_return_t IOServiceGetMatchingServices(  mach_port_t masterPort,  CFDictionaryRef matching,  io_iterator_t * existing );
-kern_return_t IOServiceAddNotification(  mach_port_t masterPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated));
+io_service_t IOServiceGetMatchingService(  mach_port_t mainPort,  CFDictionaryRef matching );
+kern_return_t IOServiceGetMatchingServices(  mach_port_t mainPort,  CFDictionaryRef matching,  io_iterator_t * existing );
+kern_return_t IOServiceAddNotification(  mach_port_t mainPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated));
 kern_return_t IOServiceAddMatchingNotification(  IONotificationPortRef notifyPort,  const io_name_t notificationType,  CFDictionaryRef matching, IOServiceMatchingCallback callback, void * refCon,  io_iterator_t * notification );
 CFMutableDictionaryRef IOServiceMatching(  const char * name );
 CFMutableDictionaryRef IOServiceNameMatching(  const char * name );
-CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t masterPort,  uint32_t options,  const char * bsdName );
-CFMutableDictionaryRef IOOpenFirmwarePathMatching(  mach_port_t masterPort,  uint32_t options,  const char * path );
+CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t mainPort,  uint32_t options,  const char * bsdName );
+CFMutableDictionaryRef IOOpenFirmwarePathMatching(  mach_port_t mainPort,  uint32_t options,  const char * path );
 CFMutableDictionaryRef IORegistryEntryIDMatching(  uint64_t entryID );
 typedef struct __DASession * DASessionRef;
 extern DASessionRef DASessionCreate( CFAllocatorRef allocator );
Index: clang/test/Analysis/retain-release.m
===
--- clang/test/Analysis/retain-release.m
+++ clang/test/Analysis/retain-release.m
@@ -233,14 +233,14 @@
 typedef io_object_t io_service_t;
 typedef struct IONotificationPort * IONotificationPortRef;
 typedef void (*IOServiceMatchingCallback)(  void * refcon,  io_iterator_t iterator );
-io_service_t IOServiceGetMatchingService(  mach_port_t masterPort,  CFDictionaryRef matching );
-kern_return_t IOServiceGetMatchingServices(  mach_port_t masterPort,  CFDictionaryRef matching,  io_iterator_t * existing );
-kern_return_t IOServiceAddNotification(  mach_port_t masterPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated)); // expected-note {{'IOServiceAddNotification' has been explicitly marked deprecated here}}
+io_service_t IOServiceGetMatchingService(  mach_port_t mainPort,  CFDictionaryRef matching );
+kern_return_t IOServiceGetMatchingServices(  mach_port_t mainPort,  CFDictionaryRef matching,  io_iterator_t * existing );
+kern_return_t IOServiceAddNotification(  mach_port_t mainPort,  const io_name_t notificationType,  CFDictionaryRef matching,  mach_port_t wakePort,  uintptr_t reference,  io_iterator_t * notification ) __attribute__((deprecated)); // expected-note {{'IOServiceAddNotification' has been explicitly marked deprecated here}}
 kern_return_t IOServiceAddMatchingNotification(  IONotificationPortRef notifyPort,  const io_name_t notificationType,  CFDictionaryRef matching, IOServiceMatchingCallback callback, void * refCon,  io_iterator_t * notification );
 CFMutableDictionaryRef IOServiceMatching(  const char * name );
 CFMutableDictionaryRef IOServiceNameMatching(  const char * name );
-CFMutableDictionaryRef IOBSDNameMatching(  mach_port_t masterPort,  uint32_t options,  const char * bsdName );

[PATCH] D113433: [NFC][clang] Inclusive language: Rename myMaster in testcase

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] As part of using inclusive language within the llvm project, this patch
replaces `_myMaster` with `_myLeader` in these testcases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113433

Files:
  clang/test/Rewriter/line-generation-test.m
  clang/test/SemaObjC/warn-direct-ivar-access.m


Index: clang/test/SemaObjC/warn-direct-ivar-access.m
===
--- clang/test/SemaObjC/warn-direct-ivar-access.m
+++ clang/test/SemaObjC/warn-direct-ivar-access.m
@@ -3,39 +3,39 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink; // expected-error {{existing instance variable 
'_isTickledPink' for property 'isTickledPink'}}
 int _myIntProp;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink; // expected-note {{property declared here}}
 @property int myIntProp;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink; // expected-note {{property 
synthesized here}}
 @synthesize myIntProp = _myIntProp;
 
 - (void) doSomething {
-_myMaster = _isTickledPink; // expected-warning {{instance variable 
'_myMaster' is being directly accessed}} \
+_myLeader = _isTickledPink; // expected-warning {{instance variable 
'_myLeader' is being directly accessed}} \
 // expected-warning {{instance variable '_isTickledPink' is being directly 
accessed}}
 }
 
 - (id) init {
-_myMaster=0;
-return _myMaster;
+_myLeader=0;
+return _myLeader;
 }
-- (void) dealloc { _myMaster = 0; }
+- (void) dealloc { _myLeader = 0; }
 @end
 
 MyObject * foo ()
 {
MyObject* p=0;
-p.isTickledPink = p.myMaster;  // ok
-   p->_isTickledPink = (*p)._myMaster; // expected-warning {{instance 
variable '_isTickledPink' is being directly accessed}} \
-// expected-warning {{instance variable '_myMaster' is being directly 
accessed}}
+p.isTickledPink = p.myLeader;  // ok
+   p->_isTickledPink = (*p)._myLeader; // expected-warning {{instance 
variable '_isTickledPink' is being directly accessed}} \
+// expected-warning {{instance variable '_myLeader' is being directly 
accessed}}
 if (p->_myIntProp) // expected-warning {{instance variable 
'_myIntProp' is being directly accessed}}
   p->_myIntProp = 0; // expected-warning {{instance variable 
'_myIntProp' is being directly accessed}}
return p->_isTickledPink; // expected-warning {{instance variable 
'_isTickledPink' is being directly accessed}}
Index: clang/test/Rewriter/line-generation-test.m
===
--- clang/test/Rewriter/line-generation-test.m
+++ clang/test/Rewriter/line-generation-test.m
@@ -7,20 +7,20 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink;
 
 - (void) doSomething {
-_myMaster = _isTickledPink;
+_myLeader = _isTickledPink;
 }
 
 @end
@@ -28,8 +28,8 @@
 MyObject * foo ()
 {
MyObject* p;
-p.isTickledPink = p.myMaster;  // ok
-   p->_isTickledPink = p->_myMaster;
+p.isTickledPink = p.myLeader;  // ok
+   p->_isTickledPink = p->_myLeader;
return p->_isTickledPink;
 }
 


Index: clang/test/SemaObjC/warn-direct-ivar-access.m
===
--- clang/test/SemaObjC/warn-direct-ivar-access.m
+++ clang/test/SemaObjC/warn-direct-ivar-access.m
@@ -3,39 +3,39 @@
 
 __attribute__((objc_root_class)) @interface MyObject {
 @public
-id _myMaster;
+id _myLeader;
 id _isTickledPink; // expected-error {{existing instance variable '_isTickledPink' for property 'isTickledPink'}}
 int _myIntProp;
 }
-@property(retain) id myMaster;
+@property(retain) id myLeader;
 @property(assign) id isTickledPink; // expected-note {{property declared here}}
 @property int myIntProp;
 @end
 
 @implementation MyObject
 
-@synthesize myMaster = _myMaster;
+@synthesize myLeader = _myLeader;
 @synthesize isTickledPink = _isTickledPink; // expected-note {{property synthesized here}}
 @synthesize myIntProp = _myIntProp;
 
 - (void) doSomething {
-_myMaster = _isTickledPink; // expected-warning {{instance variable '_myMaster' is being directly accessed}} \
+_myLeader = _isTickledPink; // expected-warning {{instance variable '_myLeader' is being directly accessed}} \
 // expected-warning 

[PATCH] D113186: [NFC] Inclusive language: Remove instances of master in URLs

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc71fbdd87b35: [NFC] Inclusive language: Remove instances of 
master in URLs (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113186/new/

https://reviews.llvm.org/D113186

Files:
  clang-tools-extra/clangd/Protocol.h
  clang/docs/ClangFormatStyleOptions.rst
  clang/docs/LibFormat.rst
  clang/docs/UsersManual.rst
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/test/OpenMP/aarch64_vfabi_NarrowestDataSize.c
  clang/test/OpenMP/aarch64_vfabi_WidestDataSize.c
  clang/www/related.html
  libcxx/utils/ci/Dockerfile
  lld/docs/WebAssembly.rst
  lld/wasm/Driver.cpp
  lld/wasm/SyntheticSections.h
  lldb/unittests/Process/minidump/Inputs/linux-x86_64.cpp
  llvm/CMakeLists.txt
  llvm/docs/CompileCudaWithLLVM.rst
  llvm/docs/Proposals/TestSuite.rst
  llvm/include/llvm/BinaryFormat/Wasm.h
  llvm/include/llvm/Object/Wasm.h
  llvm/lib/MC/WasmObjectWriter.cpp
  llvm/lib/Object/WasmObjectFile.cpp
  llvm/lib/Target/WebAssembly/README.txt
  llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp
  llvm/utils/gn/README.rst
  mlir/docs/Dialects/SPIR-V.md
  mlir/docs/LangRef.md
  mlir/docs/Rationale/Rationale.md
  mlir/docs/Rationale/RationaleGenericDAGRewriter.md
  mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
  mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
  utils/bazel/.bazelrc
  utils/bazel/README.md

Index: utils/bazel/README.md
===
--- utils/bazel/README.md
+++ utils/bazel/README.md
@@ -28,7 +28,7 @@
you don't have a checkout yet.
 2. Install Bazel at the version indicated by [.bazelversion](./.bazelversion),
following the official instructions, if you don't have it installed yet:
-   https://docs.bazel.build/versions/master/install.html.
+   https://docs.bazel.build/versions/main/install.html.
 3. `cd utils/bazel`
 4. `bazel build --config=generic_clang @llvm-project//...` (if building on Unix
with Clang). `--config=generic_gcc` and `--config=msvc` are also available.
@@ -45,7 +45,7 @@
 ```
 
 You can enable
-[disk caching](https://docs.bazel.build/versions/master/remote-caching.html#disk-cache),
+[disk caching](https://docs.bazel.build/versions/main/remote-caching.html#disk-cache),
 which will cache build results
 
 ```.bazelrc
@@ -53,7 +53,7 @@
 ```
 
 You can instruct Bazel to use a ramdisk for its sandboxing operations via
-[--sandbox_base](https://docs.bazel.build/versions/master/command-line-reference.html#flag--sandbox_base),
+[--sandbox_base](https://docs.bazel.build/versions/main/command-line-reference.html#flag--sandbox_base),
 which can help avoid IO bottlenecks for the symlink stragegy used for
 sandboxing. This is especially important with many inputs and many cores (see
 https://github.com/bazelbuild/bazel/issues/11868):
Index: utils/bazel/.bazelrc
===
--- utils/bazel/.bazelrc
+++ utils/bazel/.bazelrc
@@ -158,7 +158,7 @@
 # Platform flags:
 # The toolchain container used for execution is defined in the target indicated
 # by "extra_execution_platforms", "host_platform" and "platforms".
-# More about platforms: https://docs.bazel.build/versions/master/platforms.html
+# More about platforms: https://docs.bazel.build/versions/main/platforms.html
 build:rbe --extra_toolchains=@rbe_default//config:cc-toolchain
 build:rbe --extra_execution_platforms=@rbe_default//config:platform
 build:rbe --host_platform=@rbe_default//config:platform
Index: mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
===
--- mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
+++ mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
@@ -7,7 +7,7 @@
 //===--===//
 //
 // This file contains structs based on the LSP specification at
-// https://github.com/Microsoft/language-server-protocol/blob/master/protocol.md
+// https://github.com/Microsoft/language-server-protocol/blob/main/protocol.md
 //
 // This is not meant to be a complete implementation, new interfaces are added
 // when they're needed.
Index: mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
===
--- mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
+++ mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
@@ -13,8 +13,8 @@
 // pointed to here. However the following links contain more information about
 // ROCDL (ROCm-Device-Library)
 //
-// https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/doc/OCML.md
-// https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/doc/OCKL.md
+// 

[PATCH] D113299: [NFC] Inclusive Language: change master to main for .chm files

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added a reviewer: bollu.
Herald added subscribers: wenzhicui, wrengr, Chia-hungDuan, dcaballe, cota, 
teijeong, rdzhabarov, tatianashp, msifontes, jurahul, Kayjukh, grosul1, 
Joonsoo, liufengdb, aartbik, lucyrfox, mgester, arpith-jacob, antiagainst, 
shauheen, rriddle, mehdi_amini.
Herald added a project: Flang.
quinnp requested review of this revision.
Herald added subscribers: cfe-commits, llvm-commits, openmp-commits, 
lldb-commits, stephenneuendorffer, nicolasvasilache, jdoerfert.
Herald added projects: clang, LLDB, OpenMP, MLIR, LLVM, clang-tools-extra.

[NFC] As part of using inclusive language within the llvm project,
this patch replaces master with main when referring to `.chm` files.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113299

Files:
  clang-tools-extra/docs/doxygen.cfg.in
  clang/docs/doxygen.cfg.in
  flang/docs/doxygen.cfg.in
  lldb/docs/doxygen.cfg.in
  llvm/docs/doxygen.cfg.in
  mlir/docs/doxygen.cfg.in
  openmp/docs/doxygen.cfg.in
  openmp/runtime/doc/doxygen/config
  polly/docs/doxygen.cfg.in

Index: polly/docs/doxygen.cfg.in
===
--- polly/docs/doxygen.cfg.in
+++ polly/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: openmp/runtime/doc/doxygen/config
===
--- openmp/runtime/doc/doxygen/config
+++ openmp/runtime/doc/doxygen/config
@@ -1048,7 +1048,7 @@
 
 # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
 # controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
+# it should be included in the main .chm file (NO).
 
 GENERATE_CHI   = NO
 
Index: openmp/docs/doxygen.cfg.in
===
--- openmp/docs/doxygen.cfg.in
+++ openmp/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: mlir/docs/doxygen.cfg.in
===
--- mlir/docs/doxygen.cfg.in
+++ mlir/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: llvm/docs/doxygen.cfg.in
===
--- llvm/docs/doxygen.cfg.in
+++ llvm/docs/doxygen.cfg.in
@@ -1220,7 +1220,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: lldb/docs/doxygen.cfg.in
===
--- lldb/docs/doxygen.cfg.in
+++ lldb/docs/doxygen.cfg.in
@@ -916,7 +916,7 @@
 
 # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
 # controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
+# it should be included in the main .chm file (NO).
 
 GENERATE_CHI   = NO
 
Index: flang/docs/doxygen.cfg.in
===
--- flang/docs/doxygen.cfg.in
+++ flang/docs/doxygen.cfg.in
@@ -1222,7 +1222,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
+# YES) or that it should be included in the main .chm file ( NO).
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTMLHELP is set to YES.
 
Index: clang/docs/doxygen.cfg.in
===
--- clang/docs/doxygen.cfg.in
+++ clang/docs/doxygen.cfg.in
@@ -1219,7 +1219,7 @@
 HHC_LOCATION   =
 
 # The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master 

[PATCH] D113186: [NFC] Inclusive language: Remove instances of master in URLs

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: wenzhicui, wrengr, Chia-hungDuan, dcaballe, cota, 
teijeong, rdzhabarov, tatianashp, msifontes, jurahul, Kayjukh, grosul1, 
Joonsoo, liufengdb, aartbik, lucyrfox, mgester, arpith-jacob, antiagainst, 
shauheen, rriddle, mehdi_amini, usaxena95, kadircet, arphaman, hiraditya, 
jgravelle-google, arichardson, sbc100, mgorny, dschuff.
Herald added a reviewer: MaskRay.
Herald added a reviewer: ftynse.
quinnp requested review of this revision.
Herald added subscribers: cfe-commits, llvm-commits, libcxx-commits, 
lldb-commits, stephenneuendorffer, nicolasvasilache, aheejin.
Herald added projects: clang, LLDB, libc++, MLIR, LLVM, clang-tools-extra.
Herald added a reviewer: libc++.

[NFC] This patch fixes URLs containing "master". Old URLs were either broken or
redirecting to the new URL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113186

Files:
  clang-tools-extra/clangd/Protocol.h
  clang/docs/ClangFormatStyleOptions.rst
  clang/docs/LibFormat.rst
  clang/docs/UsersManual.rst
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/test/OpenMP/aarch64_vfabi_NarrowestDataSize.c
  clang/test/OpenMP/aarch64_vfabi_WidestDataSize.c
  clang/www/related.html
  libcxx/utils/ci/Dockerfile
  lld/docs/WebAssembly.rst
  lld/wasm/Driver.cpp
  lld/wasm/SyntheticSections.h
  lldb/unittests/Process/minidump/Inputs/linux-x86_64.cpp
  llvm/CMakeLists.txt
  llvm/docs/CompileCudaWithLLVM.rst
  llvm/docs/Proposals/TestSuite.rst
  llvm/include/llvm/BinaryFormat/Wasm.h
  llvm/include/llvm/Object/Wasm.h
  llvm/lib/MC/WasmObjectWriter.cpp
  llvm/lib/Object/WasmObjectFile.cpp
  llvm/lib/Target/WebAssembly/README.txt
  llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp
  llvm/utils/gn/README.rst
  mlir/docs/Dialects/SPIR-V.md
  mlir/docs/LangRef.md
  mlir/docs/Rationale/Rationale.md
  mlir/docs/Rationale/RationaleGenericDAGRewriter.md
  mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
  mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
  utils/bazel/.bazelrc
  utils/bazel/README.md

Index: utils/bazel/README.md
===
--- utils/bazel/README.md
+++ utils/bazel/README.md
@@ -28,7 +28,7 @@
you don't have a checkout yet.
 2. Install Bazel at the version indicated by [.bazelversion](./.bazelversion),
following the official instructions, if you don't have it installed yet:
-   https://docs.bazel.build/versions/master/install.html.
+   https://docs.bazel.build/versions/main/install.html.
 3. `cd utils/bazel`
 4. `bazel build --config=generic_clang @llvm-project//...` (if building on Unix
with Clang). `--config=generic_gcc` and `--config=msvc` are also available.
@@ -45,7 +45,7 @@
 ```
 
 You can enable
-[disk caching](https://docs.bazel.build/versions/master/remote-caching.html#disk-cache),
+[disk caching](https://docs.bazel.build/versions/main/remote-caching.html#disk-cache),
 which will cache build results
 
 ```.bazelrc
@@ -53,7 +53,7 @@
 ```
 
 You can instruct Bazel to use a ramdisk for its sandboxing operations via
-[--sandbox_base](https://docs.bazel.build/versions/master/command-line-reference.html#flag--sandbox_base),
+[--sandbox_base](https://docs.bazel.build/versions/main/command-line-reference.html#flag--sandbox_base),
 which can help avoid IO bottlenecks for the symlink stragegy used for
 sandboxing. This is especially important with many inputs and many cores (see
 https://github.com/bazelbuild/bazel/issues/11868):
Index: utils/bazel/.bazelrc
===
--- utils/bazel/.bazelrc
+++ utils/bazel/.bazelrc
@@ -158,7 +158,7 @@
 # Platform flags:
 # The toolchain container used for execution is defined in the target indicated
 # by "extra_execution_platforms", "host_platform" and "platforms".
-# More about platforms: https://docs.bazel.build/versions/master/platforms.html
+# More about platforms: https://docs.bazel.build/versions/main/platforms.html
 build:rbe --extra_toolchains=@rbe_default//config:cc-toolchain
 build:rbe --extra_execution_platforms=@rbe_default//config:platform
 build:rbe --host_platform=@rbe_default//config:platform
Index: mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
===
--- mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
+++ mlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
@@ -7,7 +7,7 @@
 //===--===//
 //
 // This file contains structs based on the LSP specification at
-// https://github.com/Microsoft/language-server-protocol/blob/master/protocol.md
+// https://github.com/Microsoft/language-server-protocol/blob/main/protocol.md
 //
 // This is not meant to be a complete implementation, new interfaces are added
 // when they're needed.
Index: mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h

[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

I think the commit message needs to be updated.

> This patch updates the vec_popcnt builtins to take a signed int as the second 
> parameter...

Should be: This patch updates the return type of the vec_popcnt builtins to 
vector unsigned...

Other than that, lgtm.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D110935: [NFC] Update vec_extract builtin signatures to take signed int.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

lgtm


Repository:
  rG LLVM Github Monorepo

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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG67a3d1e27551: [PowerPC] swdiv builtins for XL compatibility 
(authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16077,7 +16077,7 @@
*this, E, Intrinsic::sqrt,

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 375912.
quinnp added a comment.

Fixing failing test case after rebasing with https://reviews.llvm.org/D110213.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16077,7 +16077,7 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experimental_constrained_sqrt))
 .getScalarVal();
-  case 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG70391b3468b8: [PowerPC] FP compare and test XL compat 
builtins. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D106959#3021069 , @NeHuang wrote:

> Do we already have a backend test case for `fdiv` emitting a software 
> estimate when `-Ofast` is used?

I've added a testcase in `llvm/test/CodeGen/PowerPC/fdiv.ll` which goes from 
`fdiv fast` to the assembly for the software divide estimate.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 375285.
quinnp added a comment.

Added a backend testcase which goes from `fdiv fast` to software estimate. 
Added a runline in the front end testcase that sets the fast math flags.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16035,6 +16035,9 @@
*this, E, Intrinsic::sqrt,

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374891.
quinnp added a comment.

Rebase with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+return SDValue(
+

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374888.
quinnp added a comment.

Addressing nit in SemaChecking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+return 

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3b0240e6c89d: [PowerPC] Add range check for vec_genpcvm 
builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109780/new/

https://reviews.llvm.org/D109780

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is 
outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
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[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374854.
quinnp added a comment.

Rebased with main.


Repository:
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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is 
outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll:36
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE

efriedma wrote:
> quinnp wrote:
> > efriedma wrote:
> > > A "fast" fdiv never produces NaN, per LangRef.  Using fcmp like this is 
> > > fragile at best.
> > > 
> > > (Maybe you want "fdiv arcp"?)
> > Thank you, I see what you mean. I have changed it to emit a `fdiv ninf 
> > arcp` instead of a `fdiv fast`. I included the `ninf` flag because without 
> > it the compiler doesn't produce the software div estimate.
> ninf is also an issue, although maybe less likely to bite in practice.  
> Consider what happens if someone passes infinity to swdivs: the fdiv reduces 
> to poison, so the branch is undefined behavior.
We've decided to emit an `fdiv` without any fast math flags for these builtins. 
This will be safe and will emit the software estimate for `-Ofast`.


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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374847.
quinnp marked 7 inline comments as done.
quinnp added a comment.

Updatign the patch to emit a fdiv for each of the builtins without any fast 
math flags. This will be safe and will still emit a software estimate when 
`-Ofast` is used.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,54 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16035,6 +16035,9 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experimental_constrained_sqrt))
 .getScalarVal();
+  case PPC::BI__builtin_ppc_swdiv:
+  case PPC::BI__builtin_ppc_swdivs:
+return Builder.CreateFDiv(Ops[0], Ops[1], "swdiv");
   }
 }
 
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -238,6 +238,8 @@
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
   Builder.defineMacro("__addex", "__builtin_ppc_addex");
   Builder.defineMacro("__cmplxl", "__builtin_complex");
+  Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
+  Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -96,6 +96,8 @@
 BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
 BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc")
 BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
+BUILTIN(__builtin_ppc_swdiv, "ddd", "")
+BUILTIN(__builtin_ppc_swdivs, "fff", "")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")


Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,54 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374610.
quinnp added a comment.

Addressing review comment about ISelLowering of `test_data_class`.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374605.
quinnp added a comment.

Addressing some review comments.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,52 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf9912fe4eac9: [PowerPC] Add range checks for P10 Vector 
Builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1371,10 +1371,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1384,10 +1386,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1397,10 +1401,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1409,6 +1415,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 
+// for the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long 

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374563.
quinnp added a comment.

Word change. valid -> expected


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 
+// for the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374561.
quinnp added a comment.

Added a comment to the out-of-range argument test case to describe the 
behaviour.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// valid range [0,1]. A mask of 0x01 is applied to obtain an in-range value for 
+// the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374312.
quinnp added a comment.

Moving the semachecking of `test_data_class` from the function to the switch 
case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,56 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374064.
quinnp added a comment.

Separating the switch case in ISelLowering into two switch cases. One for 
`compare_exp_` and another for `test_data_class`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,56 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374000.
quinnp added a comment.

Adding a testcase where the second parameter of vec_splati_ins is out of the 
range 0,1.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,21 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- 

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG57939309501c: [PowerPC] Fix signature of lxvp and stxvp 
builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109996/new/

https://reviews.llvm.org/D109996

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -322,16 +322,16 @@
 }
 
 void testBuiltinTypes1(const __vector_pair *vpp, const __vector_pair *vp2, float f) {
-  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long long'}}
-  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long'}}
+  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long'}}
 }
 
 void testBuiltinTypes2(__vector_pair *vpp, const __vector_pair *vp2, unsigned char c) {
-  __vector_pair vp = __builtin_vsx_lxvp(6LL, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, c, vp2); // expected-error {{passing 'unsigned char' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(6L, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, c, vp2);// expected-error {{passing 'unsigned char' to parameter of incompatible type 'long'}}
 }
 
-void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long long ll, unsigned short s) {
-  __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
+void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long l, unsigned short s) {
+  __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1049,8 +1049,8 @@
 // CHECK-NEXT:ret void
 //
 void test66(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
-  __builtin_vsx_stxvp(vp, 0LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(0L, vpp);
+  __builtin_vsx_stxvp(vp, 0L, vp2);
 }
 
 // CHECK-LABEL: @test67(
@@ -1063,7 +1063,7 @@
 // CHECK-NEXT:tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
 // CHECK-NEXT:ret void
 //
-void test67(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+void test67(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
   __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
   __builtin_vsx_stxvp(vp, offset, vp2);
 }
@@ -1079,8 +1079,8 @@
 // CHECK-NEXT:ret void
 //
 void test68(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(18LL, vpp);
-  __builtin_vsx_stxvp(vp, 18LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(18L, vpp);
+  __builtin_vsx_stxvp(vp, 18L, vp2);
 }
 
 // CHECK-LABEL: @test69(
@@ -1094,8 +1094,8 @@
 // CHECK-NEXT:ret void
 //
 void test69(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(1LL, vpp);
-  __builtin_vsx_stxvp(vp, 1LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(1L, vpp);
+  __builtin_vsx_stxvp(vp, 1L, vp2);
 }
 
 // CHECK-LABEL: @test70(
@@ -1109,8 +1109,8 @@
 // CHECK-NEXT:ret void
 //
 void test70(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(42LL, vpp);
-  __builtin_vsx_stxvp(vp, 42LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(42L, vpp);
+  __builtin_vsx_stxvp(vp, 42L, vp2);
 }
 
 // CHECK-LABEL: @test71(
@@ -1124,8 +1124,8 @@
 // CHECK-NEXT:ret void
 //
 void test71(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(32768LL, vpp);
-  

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

[Quinn Pham via Phabricator via cfe-commits]

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Herald added subscribers: shchenz, kbarton, nemanjai.
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Herald added a project: clang.
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This patch changes the signature of the load and store vector pair
builtins to match their documentation. The type of the `signed long long`
argument is changed to `signed long`. This patch also changes existing testcases
to match the signature change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109996

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -322,16 +322,16 @@
 }
 
 void testBuiltinTypes1(const __vector_pair *vpp, const __vector_pair *vp2, float f) {
-  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long long'}}
-  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long'}}
+  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long'}}
 }
 
 void testBuiltinTypes2(__vector_pair *vpp, const __vector_pair *vp2, unsigned char c) {
-  __vector_pair vp = __builtin_vsx_lxvp(6LL, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, c, vp2); // expected-error {{passing 'unsigned char' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(6L, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, c, vp2);// expected-error {{passing 'unsigned char' to parameter of incompatible type 'long'}}
 }
 
-void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long long ll, unsigned short s) {
-  __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
+void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long l, unsigned short s) {
+  __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1049,8 +1049,8 @@
 // CHECK-NEXT:ret void
 //
 void test66(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
-  __builtin_vsx_stxvp(vp, 0LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(0L, vpp);
+  __builtin_vsx_stxvp(vp, 0L, vp2);
 }
 
 // CHECK-LABEL: @test67(
@@ -1063,7 +1063,7 @@
 // CHECK-NEXT:tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
 // CHECK-NEXT:ret void
 //
-void test67(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+void test67(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
   __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
   __builtin_vsx_stxvp(vp, offset, vp2);
 }
@@ -1079,8 +1079,8 @@
 // CHECK-NEXT:ret void
 //
 void test68(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(18LL, vpp);
-  __builtin_vsx_stxvp(vp, 18LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(18L, vpp);
+  __builtin_vsx_stxvp(vp, 18L, vp2);
 }
 
 // CHECK-LABEL: @test69(
@@ -1094,8 +1094,8 @@
 // CHECK-NEXT:ret void
 //
 void test69(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(1LL, vpp);
-  __builtin_vsx_stxvp(vp, 1LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(1L, vpp);
+  __builtin_vsx_stxvp(vp, 1L, vp2);
 }
 
 // CHECK-LABEL: @test70(
@@ -1109,8 +1109,8 @@
 // CHECK-NEXT:ret void
 //
 void test70(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(42LL, vpp);
-  __builtin_vsx_stxvp(vp, 42LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(42L, vpp);
+  __builtin_vsx_stxvp(vp, 42L, vp2);
 }
 
 // CHECK-LABEL: 

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 372541.
quinnp added a comment.

Removing an extra space.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3473,6 +3473,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_altivec_vcntmbb:
+  case PPC::BI__builtin_altivec_vcntmbh:
+  case PPC::BI__builtin_altivec_vcntmbw:
+  case PPC::BI__builtin_altivec_vcntmbd:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -18191,13 +18191,13 @@
 
 #define vec_cntm(__a, __mp)\
   _Generic((__a), vector unsigned char \
-   

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch adds range checking for some Power10 altivec builtins. Range
checking is done in SemaChecking.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109780

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+  {{argument value 2 is 
outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3478,6 +3478,11 @@
   case PPC::BI__builtin_altivec_vcntmbw:
   case PPC::BI__builtin_altivec_vcntmbd:
 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+  {{argument value 2 is outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3478,6 +3478,11 @@
   case PPC::BI__builtin_altivec_vcntmbw:
   case PPC::BI__builtin_altivec_vcntmbd:
 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
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[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 372479.
quinnp added a comment.

Fixing failing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+  {{argument value 2 is outside the valid range [0, 1]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3473,6 +3473,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_altivec_vcntmbb:
+  case PPC::BI__builtin_altivec_vcntmbh:
+  case PPC::BI__builtin_altivec_vcntmbw:
+  case PPC::BI__builtin_altivec_vcntmbd:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -18191,13 +18191,13 @@
 
 #define vec_cntm(__a, __mp)\
   _Generic((__a), vector unsigned char \
-  

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch adds range checking for some Power10 altivec builtins and
changes the signature of a builtin to match documentation. For `vec_cntm`,
range checking is done via SemaChecking. For `vec_splati_ins`, the second
argument is masked to extract the 0th bit so that we always receive either a `0`
or a `1`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+  {{argument value 2 is outside the valid range [0, 1]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3473,6 +3473,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_altivec_vcntmbb:
+  case PPC::BI__builtin_altivec_vcntmbh:
+  case PPC::BI__builtin_altivec_vcntmbw:
+  case PPC::BI__builtin_altivec_vcntmbd:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
Index: 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 372243.
quinnp added a comment.

Adding SemaChecking for the first argument of __builitn_ppc_test_data_class so
the llvm_unreachable in CGBuiltin is actually unreachable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10382,6 +10382,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo:
+  case Intrinsic::ppc_test_data_class_d:
+  case Intrinsic::ppc_test_data_class_f: {
+unsigned CmprOpc = PPC::XSCMPEXPDP;
+SDValue Op1 = Op.getOperand(1);
+SDValue Op2 = Op.getOperand(2);
+unsigned Pred;
+switch (IntrinsicID) {
+

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch is in a series of patches to provide builtins for
compatability with the XL compiler. This patch adds builtins for compare
exponent and test data class operations on floating point values.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10382,6 +10382,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo:
+  case Intrinsic::ppc_test_data_class_d:
+  case Intrinsic::ppc_test_data_class_f: {
+unsigned CmprOpc = PPC::XSCMPEXPDP;
+SDValue 

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked an inline comment as done.
quinnp added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll:36
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE

efriedma wrote:
> A "fast" fdiv never produces NaN, per LangRef.  Using fcmp like this is 
> fragile at best.
> 
> (Maybe you want "fdiv arcp"?)
Thank you, I see what you mean. I have changed it to emit a `fdiv ninf arcp` 
instead of a `fdiv fast`. I included the `ninf` flag because without it the 
compiler doesn't produce the software div estimate.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106959/new/

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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 363189.
quinnp added a comment.

Addressing review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/O3-pipeline.ll
===
--- llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -63,6 +63,8 @@
 ; CHECK-NEXT:   Expand vector predication intrinsics
 ; CHECK-NEXT:   Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:   Expand reduction intrinsics
+; CHECK-NEXT:   Lower Checked Floating Point Arithmetic
+; CHECK-NEXT:   Dominator Tree Construction
 ; CHECK-NEXT:   Natural Loop Information
 ; CHECK-NEXT:   CodeGen Prepare
 ; CHECK-NEXT:   Dominator Tree Construction
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv ninf arcp double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv ninf arcp float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 362400.
quinnp added a comment.

Fixing a failing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/O3-pipeline.ll
===
--- llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -63,6 +63,8 @@
 ; CHECK-NEXT:   Expand vector predication intrinsics
 ; CHECK-NEXT:   Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:   Expand reduction intrinsics
+; CHECK-NEXT:   Lower Checked Floating Point Arithmetic
+; CHECK-NEXT:   Dominator Tree Construction
 ; CHECK-NEXT:   Natural Loop Information
 ; CHECK-NEXT:   CodeGen Prepare
 ; CHECK-NEXT:   Dominator Tree Construction
@@ -206,4 +208,4 @@
 
 define void @f() {
   ret void
-}
\ No newline at end of file
+}
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv fast double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility]

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, mgorny, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch is in a series of patches to provide builtins for compatibility with
the XL compiler. This patch adds software divide builtins with checking.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv fast double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -125,6 +125,7 @@
   initializePPCLowerMASSVEntriesPass(PR);
   initializePPCExpandAtomicPseudoPass(PR);
   initializeGlobalISel(PR);
+  initializePPCLowerCheckedFPArithPass(PR);
 }
 
 static bool isLittleEndianTriple(const Triple ) {
@@ -447,6 +448,8 @@
   }
 
   TargetPassConfig::addIRPasses();
+
+  addPass(createPPCLowerCheckedFPArithPass());
 }
 
 bool PPCPassConfig::addPreISel() {
Index: 

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D103986#2893177 , @DavidSpickett 
wrote:

> You missed a REQUIRES for the llvm test, I added one in: 
> https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5
>
> So if you see Arm-AArch64 quick bot failures, that was the reason.

Right, sorry about that. Thank you, I will also move the test to 
`llvm/test/CodeGen/PowerPC`


Repository:
  rG LLVM Github Monorepo

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[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe002d251dd34: [PowerPC] Floating Point Builtins for XL 
Compat. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3267,6 +3268,7 @@
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
   (STXSIWX f64:$XT, ForceXForm:$dst)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: 

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 360408.
quinnp added a comment.

Rebasing to ToT.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3267,6 +3268,7 @@
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
   (STXSIWX f64:$XT, ForceXForm:$dst)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
---