[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 abandoned this revision.
fakepaper56 added a comment.

Closed it and create a PR https://github.com/llvm/llvm-project/pull/66043 for 
version 0.3.1.


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 planned changes to this revision.
fakepaper56 added a comment.
Herald added a subscriber: sunshaoce.

The spec does some change, I need to sync with the spec.


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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550998.
fakepaper56 added a comment.

Address jrtc27's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550987.
fakepaper56 added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550578.
fakepaper56 added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:88
+
+let Predicates = [HasStdExtZicfiss, HasStdExtC] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 
in

craig.topper wrote:
> Is it compatible with Zca?
The spec does not mention it is incompatible with Zca. I think I need to enable 
c.push/c.popchk for Zca.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Yeting Kuo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG818e76d6f2dd: [RISCV] Add MC layer support for Zicfilp. 
(authored by fakepaper56).

Changed prior to commit:
  https://reviews.llvm.org/D157362?vs=550089=550562#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157362/new/

https://reviews.llvm.org/D157362

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfilp-invalid.s
  llvm/test/MC/RISCV/zicfilp-valid.s

Index: llvm/test/MC/RISCV/zicfilp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-valid.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: lpad 22
+# CHECK-ASM: auipc zero, 22
+# CHECK-ASM: encoding: [0x17,0x60,0x01,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'Zicfilp' (Landing pad)
+lpad 22
Index: llvm/test/MC/RISCV/zicfilp-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-NO-EXT: immediate must be an integer in the range [0, 1048575]
+lpad 1048576
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -299,3 +299,6 @@
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute  5, "rv32i2p1_xcvbi1p0"
+
+.attribute arch, "rv32i_zicfilp0p2"
+# CHECK: attribute  5, "rv32i2p1_zicfilp0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -86,6 +86,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -174,6 +175,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
 
 ; CHECK: .attribute 4, 16
 
@@ -262,6 +264,7 @@
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -349,6 +352,7 @@
 ; RV64ZVFBFMIN: .attribute 5, 

[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550089.
fakepaper56 added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157362/new/

https://reviews.llvm.org/D157362

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfilp-invalid.s
  llvm/test/MC/RISCV/zicfilp-valid.s

Index: llvm/test/MC/RISCV/zicfilp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-valid.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: lpad 22
+# CHECK-ASM: auipc zero, 22
+# CHECK-ASM: encoding: [0x17,0x60,0x01,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'Zicfilp' (Landing pad)
+lpad 22
Index: llvm/test/MC/RISCV/zicfilp-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-NO-EXT: immediate must be an integer in the range [0, 1048575]
+lpad 1048576
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -299,3 +299,6 @@
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute  5, "rv32i2p1_xcvbi1p0"
+
+.attribute arch, "rv32i_zicfilp0p2"
+# CHECK: attribute  5, "rv32i2p1_zicfilp0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -86,6 +86,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -174,6 +175,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
 
 ; CHECK: .attribute 4, 16
 
@@ -262,6 +264,7 @@
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -349,6 +352,7 @@
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550083.
fakepaper56 added a comment.

Update docs/RISCVUsage.rst to move zicfiss to experimental extension.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 550079.
fakepaper56 added a comment.

Update docs/RISCVUsage.rst.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)

[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 549262.
fakepaper56 added a comment.

Update docs/RISCVUsage.rst.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157362/new/

https://reviews.llvm.org/D157362

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfilp-invalid.s
  llvm/test/MC/RISCV/zicfilp-valid.s

Index: llvm/test/MC/RISCV/zicfilp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-valid.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: auipc zero, 22
+# CHECK-ASM: encoding: [0x17,0x60,0x01,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'Zicfilp' (Landing pad)
+lpad 22
Index: llvm/test/MC/RISCV/zicfilp-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-NO-EXT: immediate must be an integer in the range [0, 1048575]
+lpad 1048576
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -299,3 +299,6 @@
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute  5, "rv32i2p1_xcvbi1p0"
+
+.attribute arch, "rv32i_zicfilp0p2"
+# CHECK: attribute  5, "rv32i2p1_zicfilp0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -86,6 +86,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -174,6 +175,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
 
 ; CHECK: .attribute 4, 16
 
@@ -262,6 +264,7 @@
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -349,6 +352,7 @@
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 549251.
fakepaper56 added a comment.

Update docs/RISCVUsage.rst.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added reviewers: craig.topper, frasercrmck, rogfer01, reames, asb, 
luke.
fakepaper56 marked an inline comment as done.
fakepaper56 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:56
+let Predicates = [HasStdExtZicfiss] in {
+def SSLoadX1: RV_SSPop<0b1, 0b0, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00101, 0b0, "ssload", "x5">;

fakepaper56 wrote:
> craig.topper wrote:
> > Need to be able to parse with `ra` instead of x1 and `t0` instead of x5. 
> > 
> > I think you might need a new Operand type so the parse can parse it as a 
> > register.
> > Need to be able to parse with ra instead of x1 and t0 instead of x5.
> Actually, we can parse `ssload ra` in llvm/test/MC/RISCV/zicfiss-valid.s, but 
> the code indeed can not print `ssload ra`. I have tried to define `ssload` 
> and `sspopchk` separately, but it caused decode conflict.
The problem is fixed in latest update.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 548873.
fakepaper56 added a comment.

Make asmprinter capable to print alias register name for 
ssload/sspopchk/c.sspush/c.sspopchk.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed 

[PATCH] D157362: [RISCV] Add Zicfilp extension.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 548088.
fakepaper56 added a comment.

Also support pseudo instruction lpad.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157362/new/

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfilp-invalid.s
  llvm/test/MC/RISCV/zicfilp-valid.s

Index: llvm/test/MC/RISCV/zicfilp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-valid.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfilp < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfilp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: auipc zero, 22
+# CHECK-ASM: encoding: [0x17,0x60,0x01,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'Zicfilp' (Landing pad)
+lpad 22
Index: llvm/test/MC/RISCV/zicfilp-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfilp-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicfilp -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-NO-EXT: immediate must be an integer in the range [0, 1048575]
+lpad 1048576
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -299,3 +299,6 @@
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute  5, "rv32i2p1_xcvbi1p0"
+
+.attribute arch, "rv32i_zicfilp0p2"
+# CHECK: attribute  5, "rv32i2p1_zicfilp0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -86,6 +86,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -174,6 +175,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
 
 ; CHECK: .attribute 4, 16
 
@@ -262,6 +264,7 @@
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -349,6 +352,7 @@
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, 

[PATCH] D157362: [RISCV] Add Zicfilp extension.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
fakepaper56 added reviewers: craig.topper, reames, frasercrmck, rogfer01, asb.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, jdoerfert, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
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Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157362

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -299,3 +299,6 @@
 
 .attribute arch, "rv32i_xcvbi"
 # CHECK: attribute  5, "rv32i2p1_xcvbi1p0"
+
+.attribute arch, "rv32i_zicfilp0p2"
+# CHECK: attribute  5, "rv32i2p1_zicfilp0p2"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -86,6 +86,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -174,6 +175,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
 
 ; CHECK: .attribute 4, 16
 
@@ -262,6 +264,7 @@
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -349,6 +352,7 @@
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
 ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
+; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p2"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -647,6 +647,13 @@
"other extensions: Zvks and Zvkg.",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
 
+def FeatureStdExtZicfilp
+: SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
+   "'Zicfilp' (Landing pad)">;
+def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicfilp),
+ "'Zicfilp' (Landing pad)">;
+
 def FeatureStdExtZicond
 : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
"'Zicond' (Integer Conditional Operations)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -167,6 +167,7 @@
 {"zfa", RISCVExtensionVersion{0, 2}},
 {"zfbfmin", RISCVExtensionVersion{0, 8}},
 
+{"zicfilp", RISCVExtensionVersion{0, 2}},
 {"zicond", RISCVExtensionVersion{1, 0}},
 
 {"zihintntl", RISCVExtensionVersion{0, 2}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 548027.
fakepaper56 added a comment.

Bump to 0.2 and address part of comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.sspush x1
+

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:56
+let Predicates = [HasStdExtZicfiss] in {
+def SSLoadX1: RV_SSPop<0b1, 0b0, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00101, 0b0, "ssload", "x5">;

craig.topper wrote:
> Need to be able to parse with `ra` instead of x1 and `t0` instead of x5. 
> 
> I think you might need a new Operand type so the parse can parse it as a 
> register.
> Need to be able to parse with ra instead of x1 and t0 instead of x5.
Actually, we can parse `ssload ra` in llvm/test/MC/RISCV/zicfiss-valid.s, but 
the code indeed can not print `ssload ra`. I have tried to define `ssload` and 
`sspopchk` separately, but it caused decode conflict.


Repository:
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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 544228.
fakepaper56 added a comment.

Address Craig's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 544212.
fakepaper56 marked 5 inline comments as done.
fakepaper56 added a comment.

Use RVInstI for SS_Push.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 544209.
fakepaper56 added a comment.

Address Craig's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 543857.
fakepaper56 added a comment.

Fix bugs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfisslp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 542785.
fakepaper56 added a comment.

Make the patch only focus on Zicfiss.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfiss-invalid.s
  llvm/test/MC/RISCV/zicfiss-valid.s

Index: llvm/test/MC/RISCV/zicfiss-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,110 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfisslp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 541477.
fakepaper56 added a comment.
Herald added a subscriber: wangpc.

Update instruction information and mark ssp as reserved register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfisslp-invalid.s
  llvm/test/MC/RISCV/zicfisslp-valid.s

Index: llvm/test/MC/RISCV/zicfisslp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfisslp-valid.s
@@ -0,0 +1,120 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# 

[PATCH] D152793: [RISCV] Add MC layer support for Zicfisslp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added a comment.

The patch might be too early to be posted. My idea is to make people easier to 
develop shadow-stack/landing-pads.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152793/new/

https://reviews.llvm.org/D152793

___
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[PATCH] D152793: [RISCV] Add MC layer support for Zicfisslp.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
Herald added subscribers: jobnoorman, luke, vporpo, VincentWu, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
fakepaper56 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

The patch adds the instructions in Zicfisslp extension. Zicfisslp extension is
to support shadow stack and landing pad for better control flow integrity.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152793

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/zicfisslp-invalid.s
  llvm/test/MC/RISCV/zicfisslp-valid.s

Index: llvm/test/MC/RISCV/zicfisslp-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/zicfisslp-valid.s
@@ -0,0 +1,120 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush x5
+
+# 

[PATCH] D149334: [RISCV] Enable strict fp for RISC-V in clang.

[Yeting Kuo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGfa53ce0faaa0: [RISCV] Enable strict fp for RISC-V in clang. 
(authored by fakepaper56).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149334/new/

https://reviews.llvm.org/D149334

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/fpconstrained.c


Index: clang/test/CodeGen/RISCV/fpconstrained.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/fpconstrained.c
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -triple riscv64 -frounding-math 
-ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=FPMODELSTRICT
+// RUN: %clang_cc1 -triple riscv64 -ffp-contract=fast -emit-llvm -o - %s | 
FileCheck %s -check-prefix=PRECISE
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -emit-llvm 
-o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -emit-llvm -o - %s | FileCheck 
%s -check-prefix=FASTNOCONTRACT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=ignore -emit-llvm -o - %s | FileCheck %s 
-check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=EXCEPT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=MAYTRAP
+
+// Test strict-fp support in RISC-V.
+
+float f0, f1, f2;
+
+void foo(void) {
+  // CHECK-LABEL: define {{.*}}void @foo()
+
+  // MAYTRAP: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
+  // EXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
+  // FPMODELSTRICT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, 
float %{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  // STRICTEXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  // STRICTNOEXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, 
float %{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.ignore")
+  // PRECISE: fadd contract float %{{.*}}, %{{.*}}
+  // FAST: fadd fast
+  // FASTNOCONTRACT: fadd reassoc nnan ninf nsz arcp afn float
+  f0 = f1 + f2;
+
+  // CHECK: ret
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -41,6 +41,7 @@
 HasRISCVVTypes = true;
 MCountName = "_mcount";
 HasFloat16 = true;
+HasStrictFP = true;
   }
 
   bool setCPU(const std::string ) override {


Index: clang/test/CodeGen/RISCV/fpconstrained.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/fpconstrained.c
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -triple riscv64 -frounding-math -ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=FPMODELSTRICT
+// RUN: %clang_cc1 -triple riscv64 -ffp-contract=fast -emit-llvm -o - %s | FileCheck %s -check-prefix=PRECISE
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -emit-llvm -o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -emit-llvm -o - %s | FileCheck %s -check-prefix=FASTNOCONTRACT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=ignore -emit-llvm -o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=EXCEPT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=MAYTRAP
+
+// Test strict-fp support in RISC-V.
+
+float f0, f1, f2;
+
+void foo(void) {
+  // CHECK-LABEL: define {{.*}}void @foo()
+
+  // MAYTRAP: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
+  // EXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
+  // FPMODELSTRICT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float %{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  // STRICTEXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float %{{.*}}, metadata !"round.dynamic", metadata 

[PATCH] D149334: [RISCV] Enable strict fp for RISC-V in clang.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
fakepaper56 added reviewers: craig.topper, reames, frasercrmck, rogfer01.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
fakepaper56 requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149334

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/fpconstrained.c


Index: clang/test/CodeGen/RISCV/fpconstrained.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/fpconstrained.c
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -triple riscv64 -frounding-math 
-ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=FPMODELSTRICT
+// RUN: %clang_cc1 -triple riscv64 -ffp-contract=fast -emit-llvm -o - %s | 
FileCheck %s -check-prefix=PRECISE
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -emit-llvm 
-o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -emit-llvm -o - %s | FileCheck 
%s -check-prefix=FASTNOCONTRACT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=ignore -emit-llvm -o - %s | FileCheck %s 
-check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=EXCEPT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast 
-ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm 
-o - %s | FileCheck %s -check-prefix=MAYTRAP
+
+// Test strict-fp support in RISC-V.
+
+float f0, f1, f2;
+
+void foo(void) {
+  // CHECK-LABEL: define {{.*}}void @foo()
+
+  // MAYTRAP: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
+  // EXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
+  // FPMODELSTRICT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, 
float %{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  // STRICTEXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 
%{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  // STRICTNOEXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, 
float %{{.*}}, metadata !"round.dynamic", metadata !"fpexcept.ignore")
+  // PRECISE: fadd contract float %{{.*}}, %{{.*}}
+  // FAST: fadd fast
+  // FASTNOCONTRACT: fadd reassoc nnan ninf nsz arcp afn float
+  f0 = f1 + f2;
+
+  // CHECK: ret
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -41,6 +41,7 @@
 HasRISCVVTypes = true;
 MCountName = "_mcount";
 HasFloat16 = true;
+HasStrictFP = true;
   }
 
   bool setCPU(const std::string ) override {


Index: clang/test/CodeGen/RISCV/fpconstrained.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/fpconstrained.c
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -triple riscv64 -frounding-math -ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=FPMODELSTRICT
+// RUN: %clang_cc1 -triple riscv64 -ffp-contract=fast -emit-llvm -o - %s | FileCheck %s -check-prefix=PRECISE
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -emit-llvm -o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -emit-llvm -o - %s | FileCheck %s -check-prefix=FASTNOCONTRACT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=ignore -emit-llvm -o - %s | FileCheck %s -check-prefix=FAST
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=strict -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=EXCEPT
+// RUN: %clang_cc1 -triple riscv64 -ffast-math -ffp-contract=fast -ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=MAYTRAP
+
+// Test strict-fp support in RISC-V.
+
+float f0, f1, f2;
+
+void foo(void) {
+  // CHECK-LABEL: define {{.*}}void @foo()
+
+  // MAYTRAP: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
+  // EXCEPT: llvm.experimental.constrained.fadd.f32(float %{{.*}}, float 

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

[Yeting Kuo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbd9c0f082b20: [RISCV] Add Svpbmt extension support. 
(authored by fakepaper56).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140692/new/

https://reviews.llvm.org/D140692

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/TargetParser/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll


Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck 
--check-prefix=RV32ZCA %s
 
@@ -77,6 +78,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck 
--check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck 
--check-prefix=RV64XTHEADVDOT %s
@@ -121,6 +123,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
 
@@ -162,6 +165,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADVDOT: .attribute 5, 
"rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
Index: llvm/lib/TargetParser/RISCVISAInfo.cpp
===
--- llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@
 {"zicbop", RISCVExtensionVersion{1, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
+{"svpbmt", RISCVExtensionVersion{1, 0}},
 {"svinval", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@
 : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
 
+def FeatureStdExtSvpbmt
+: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+   "'Svpbmt' (Page-Based Memory Types)">;
+
 def FeatureStdExtSvinval
 : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache 
Invalidation)">;
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -53,6 +53,7 @@
  ``F``Supported
  ``M``Supported
  ``Svinval``  Assembly Support
+ ``Svpbmt``   Supported
  ``V``Supported
  ``Zba``  Supported
  ``Zbb``  Supported
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 // CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
 // CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
 // RUN: -o - | FileCheck 

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 485447.
fakepaper56 added a comment.

Suppress lint warning.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140692/new/

https://reviews.llvm.org/D140692

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/TargetParser/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll


Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck 
--check-prefix=RV32ZCA %s
 
@@ -77,6 +78,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck 
--check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck 
--check-prefix=RV64XTHEADVDOT %s
@@ -121,6 +123,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
 
@@ -162,6 +165,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADVDOT: .attribute 5, 
"rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
Index: llvm/lib/TargetParser/RISCVISAInfo.cpp
===
--- llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@
 {"zicbop", RISCVExtensionVersion{1, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
+{"svpbmt", RISCVExtensionVersion{1, 0}},
 {"svinval", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@
 : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
 
+def FeatureStdExtSvpbmt
+: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+   "'Svpbmt' (Page-Based Memory Types)">;
+
 def FeatureStdExtSvinval
 : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache 
Invalidation)">;
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -53,6 +53,7 @@
  ``F``Supported
  ``M``Supported
  ``Svinval``  Assembly Support
+ ``Svpbmt``   Supported
  ``V``Supported
  ``Zba``  Supported
  ``Zbb``  Supported
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 // CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
 // CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
 // CHECK-SVNAPOT-EXT: __riscv_svnapot 100{{$}}
 
+// RUN: %clang -target riscv32 

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 485446.
fakepaper56 added a comment.

Fix typoes and add svpbmt into llvm/docs/RISCVUsage.rst.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140692/new/

https://reviews.llvm.org/D140692

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/TargetParser/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll


Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck 
--check-prefix=RV32ZCA %s
 
@@ -77,6 +78,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck 
--check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck 
--check-prefix=RV64XTHEADVDOT %s
@@ -121,6 +123,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
 
@@ -162,6 +165,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADVDOT: .attribute 5, 
"rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
Index: llvm/lib/TargetParser/RISCVISAInfo.cpp
===
--- llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@
 {"zicbop", RISCVExtensionVersion{1, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
+{"svpbmt", RISCVExtensionVersion{1, 0}},
 {"svinval", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@
 : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
 
+def FeatureStdExtSvpbmt
+: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+   "'Svpbmt' (Page-Based Memory Types)">;
+
 def FeatureStdExtSvinval
 : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache 
Invalidation)">;
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -53,6 +53,7 @@
  ``F``Supported
  ``M``Supported
  ``Svinval``  Assembly Support
+ ``Svpbmt``   Supported
  ``V``Supported
  ``Zba``  Supported
  ``Zbb``  Supported
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 // CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
 // CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
 // CHECK-SVNAPOT-EXT: __riscv_svnapot 100{{$}}
 
+// RUN: 

[PATCH] D140692: [RISCV] Add Svbmpt extension support.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
fakepaper56 added reviewers: kito-cheng, craig.topper, asb, reames.
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Spec of Svbmpt: 
https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140692

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/TargetParser/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll


Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck 
--check-prefix=RV32ZCA %s
 
@@ -77,6 +78,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck 
--check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck 
--check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck 
--check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck 
--check-prefix=RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck 
--check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck 
--check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck 
--check-prefix=RV64XTHEADVDOT %s
@@ -121,6 +123,7 @@
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
 
@@ -162,6 +165,7 @@
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADVDOT: .attribute 5, 
"rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
Index: llvm/lib/TargetParser/RISCVISAInfo.cpp
===
--- llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@
 {"zicbop", RISCVExtensionVersion{1, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
+{"svpbmt", RISCVExtensionVersion{1, 0}},
 {"svinval", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@
 : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
 
+def FeatureStdExtSvpbmt
+: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+   "'Svpbmt' (Page-Based Memory Types)">;
+
 def FeatureStdExtSvinval
 : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache 
Invalidation)">;
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 // CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
 // CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
 // RUN: -o - | FileCheck 

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");

khchen wrote:
> I feel this logic is not clear for reader, maybe you should add comment to 
> say why the return type -1 are load intrinsics?
You are right. Maybe I could rewrite the message of assertion to "RVVI should 
be vector load intrinsic, we don't support this feature for stores now."?


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Yeting Kuo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG939352b6ec31: [RISCV][Clang] Teach RISCVEmitter to generate 
BitCast for pointer operands. (authored by fakepaper56).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129043/new/

https://reviews.llvm.org/D129043

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "  Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "], ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-  }] in {
+  UnMaskedPolicy = HasPassthruOperand in {
 foreach type = types in {
-  def : RVVBuiltin<"v", "vPCet", type>;
+  def : RVVOutBuiltin<"v", "vPCet", type>;
   if !not(IsFloat.val) then {
-def : RVVBuiltin<"Uv", "UvPCUet", type>;
+def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
   }
 }
   }
 }
 
 multiclass RVVIndexedLoad {
-  let ManualCodegen = [{
-IntrinsicTypes = 

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 updated this revision to Diff 441943.
fakepaper56 added a comment.

Align output code in riscv_vector_builtin_cg.inc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129043/new/

https://reviews.llvm.org/D129043

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "  Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "], ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-  }] in {
+  UnMaskedPolicy = HasPassthruOperand in {
 foreach type = types in {
-  def : RVVBuiltin<"v", "vPCet", type>;
+  def : RVVOutBuiltin<"v", "vPCet", type>;
   if !not(IsFloat.val) then {
-def : RVVBuiltin<"Uv", "UvPCUet", type>;
+def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
   }
 }
   }
 }
 
 multiclass RVVIndexedLoad {
-  let ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
-Ops[0] = 

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
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fakepaper56 requested review of this revision.
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Herald added a project: clang.

RVV C intrinsics use pointers to scalar for base address and their corresponding
IR intrinsics but use pointers to vector. It makes some vector load intrinsics
need specific ManualCodegen and MaskedManualCodegen to just add bitcast for
transforming to IR.

For simplifying riscv_vector.td, the patch make RISCVEmitter detect pointer
operands and bitcast them.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129043

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "],ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-

[PATCH] D128624: [RISCV] Zero immediate for vget/vset builtins to match vector.insert/extract intrinsics.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added a comment.

LGTM


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[PATCH] D126742: [RISCV][Clang] Support RVV policy functions.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added inline comments.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:329
+
+  auto appendPolicySuffix = [&](std::string suffix) {
+Name += suffix;

Using `const std::string `.



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:876
+
+  auto appendPolicySuffix = [&](std::string suffix) {
+Name += suffix;

Using `const std::string `.


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[PATCH] D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added a comment.

LGTM.


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[PATCH] D117199: [RISCV] Add missing namespace (NFC)

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 closed this revision.
fakepaper56 added a comment.
Herald added subscribers: pcwang-thead, eopXD.

The patch content is in D119727 .


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[PATCH] D117199: [RISCV] Add missing namespace (NFC)

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added a comment.

The main reason I want to add the prefix "llvm::" is all None in the files are 
"llvm::None" form. But also it is more feasible when we want to add a variable 
name 'None' in the file.


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[PATCH] D117199: [RISCV] Add missing namespace (NFC)

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 created this revision.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
fakepaper56 requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -297,7 +297,7 @@
   }
   // Illegal vscale result would be less than 1
   if (Log2ScaleResult < 0)
-return None;
+return llvm::None;
   return 1 << Log2ScaleResult;
 }
 


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -297,7 +297,7 @@
   }
   // Illegal vscale result would be less than 1
   if (Log2ScaleResult < 0)
-return None;
+return llvm::None;
   return 1 << Log2ScaleResult;
 }
 
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