[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes abandoned this revision. c-rhodes added a comment. I've posted a prototype D85128 with an alternative implementation, given it's quite different to this patch I've posted it as a separate patch and am abandoning this one. See new patch for more

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added inline comments. Comment at: clang/lib/CodeGen/CGExpr.cpp:152 + Align, Name, + /*ArraySize=*/nullptr, Alloca); c-rhodes wrote: > efriedma wrote: > > Do we need to bitcast the result of CreateTempAlloca to a pointer to the > > array

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes marked an inline comment as done. c-rhodes added inline comments. Comment at: clang/lib/CodeGen/CGExpr.cpp:152 + Align, Name, + /*ArraySize=*/nullptr, Alloca); efriedma wrote: > Do we need to bitcast the result of CreateTempAlloca to a

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added inline comments. Comment at: clang/lib/CodeGen/CGExpr.cpp:152 + Align, Name, + /*ArraySize=*/nullptr, Alloca); Do we need to bitcast the result of CreateTempAlloca to a pointer to the array type? I'm concerned that we might miss a

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes marked an inline comment as done. c-rhodes added inline comments. Comment at: clang/lib/CodeGen/CodeGenTypes.h:138 + llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false, +bool EnforceFixedLengthSVEAttribute = false);

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes updated this revision to Diff 279265. c-rhodes added a comment. Change the default for `EnforceFixedLengthSVEAttribute`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83553/new/ https://reviews.llvm.org/D83553 Files: clang/lib/CodeGen/CGExpr.cpp

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added inline comments. Comment at: clang/lib/CodeGen/CodeGenTypes.h:138 + llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false, +bool EnforceFixedLengthSVEAttribute = false); c-rhodes wrote: > efriedma

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes marked 5 inline comments as done. c-rhodes added inline comments. Comment at: clang/lib/CodeGen/CodeGenTypes.h:138 + llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false, +bool EnforceFixedLengthSVEAttribute = false);

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes updated this revision to Diff 278466. c-rhodes added a comment. Changes: - Rebased. - Added comments for args in calls to `ConvertTypeForMem` when `EnforceFixedLengthSVEAttribute` is set and documented `EnforceFixedLengthSVEAttribute`. -

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added a comment. In D83553#2151591 , @sdesmalen wrote: > In D83553#2148429 , @efriedma wrote: > > > > If you mean alloca's for single vectors > > > > I was really referring to the IR values themselves, not

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

sdesmalen added a comment. In D83553#2148429 , @efriedma wrote: > > If you mean alloca's for single vectors > > I was really referring to the IR values themselves, not the memory > representation. Since the width of the vectors is known, you could emit

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added a comment. > If you mean alloca's for single vectors I was really referring to the IR values themselves, not the memory representation. Since the width of the vectors is known, you could emit IR without any mention of scalable types at all (assuming the backend was extended to

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

sdesmalen added a comment. In D83553#2145227 , @efriedma wrote: > What's the tradeoff of representing these in IR as vscale'ed vector types, as > opposed to fixed-wdith vector types? If you mean alloca's for single vectors, then that's partly to do

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

efriedma added a comment. What's the tradeoff of representing these in IR as vscale'ed vector types, as opposed to fixed-wdith vector types? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83553/new/ https://reviews.llvm.org/D83553 ___

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes updated this revision to Diff 277043. c-rhodes added a comment. Changes: - Use fixed-length instead of fixed-width in naming. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83553/new/ https://reviews.llvm.org/D83553 Files: clang/lib/CodeGen/CGExpr.cpp

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

c-rhodes created this revision. c-rhodes added reviewers: sdesmalen, rsandifo-arm, efriedma, cameron.mcinally, ctetreau. Herald added subscribers: danielkiss, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. This patch implements codegen for the