[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5475 + if (IndexVT.getVectorElementType() == MVT::i64 && XLenVT == MVT::i32) { +report_fatal_error("The V extension does not support EEW=64 for index " craig.topper

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5475 + if (IndexVT.getVectorElementType() == MVT::i64 && XLenVT == MVT::i32) { +report_fatal_error("The V extension does not support EEW=64 for index " Can we

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:179 const std::vector , - StringRef RequiredExtension, unsigned NF); + const std::vector RequiredExtensions, unsigned NF); ~RVVIntrinsic() =

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:179 const std::vector , - StringRef RequiredExtension, unsigned NF); + const std::vector RequiredExtensions, unsigned NF); ~RVVIntrinsic() =

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:680 foreach type = TypeList in { -foreach eew_list = EEWList in { +foreach eew_list = Xlen32EEWList in { defvar eew = eew_list[0];

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

HsiangKai added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:680 foreach type = TypeList in { -foreach eew_list = EEWList in { +foreach eew_list = Xlen32EEWList in { defvar eew = eew_list[0]; There is

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:555 +defvar Xlen32EEWList = [["8", "(Log2EEW:3)"], +["16", "(Log2EEW:4)"], frasercrmck wrote: > jrtc27 wrote: > > Ignoring whether the change is

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

frasercrmck added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:555 +defvar Xlen32EEWList = [["8", "(Log2EEW:3)"], +["16", "(Log2EEW:4)"], jrtc27 wrote: > Ignoring whether the change is actually correct, this

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:693 +let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask", +RequiredExtensions = ["Xlen64"] in { +def: RVVBuiltin<"v", "vPCe" # eew64_type #

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added a comment. In D106518#2895613 , @jacquesguan wrote: > In D106518#2895445 , @craig.topper > wrote: > >> Why do they need to be disabled? Doesn’t the spec define them to truncate? > > In the

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jacquesguan added a comment. In D106518#2895445 , @craig.topper wrote: > Why do they need to be disabled? Doesn’t the spec define them to truncate? In the 1.0-rc1, 18.2: The V extension supports all vector load and store instructions (Section Vector

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

jrtc27 added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:555 +defvar Xlen32EEWList = [["8", "(Log2EEW:3)"], +["16", "(Log2EEW:4)"], Ignoring whether the change is actually correct, this should be capitalised

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added a comment. Why do they need to be disabled? Doesn’t the spec define them to truncate? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___