[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-25 Thread Philip Reames via Phabricator via cfe-commits
reames added a comment. In D149495#4373796 , @michaelmaitland wrote: > In D149495#4373768 , @reames wrote: > >> Let's go ahead and land this as is, we can rework the stylistic pieces once >> the linked patches

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-25 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland added a comment. In D149495#4373768 , @reames wrote: > Let's go ahead and land this as is, we can rework the stylistic pieces once > the linked patches land. This has landed in

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-25 Thread Philip Reames via Phabricator via cfe-commits
reames added a comment. Let's go ahead and land this as is, we can rework the stylistic pieces once the linked patches land. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/ https://reviews.llvm.org/D149495

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-23 Thread Wang Pengcheng via Phabricator via cfe-commits
pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. michaelmaitland wrote: > michaelmaitland wrote: > >

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-23 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. michaelmaitland wrote: > pcwang-thead wrote: > >

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1a855819a87f: [RISCV] Add support for V extenstion in SiFive7 (authored by michaelmaitland). Changed prior to commit:

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41 +// Helper function to get the largest LMUL from MxList +// Precondition: MxList is sorted in ascending LMUL order. pcwang-thead wrote: > So, are we going to discard

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland updated this revision to Diff 521024. michaelmaitland marked 2 inline comments as done. michaelmaitland added a comment. Use defvar in subroutines. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-10 Thread Wang Pengcheng via Phabricator via cfe-commits
pcwang-thead accepted this revision. pcwang-thead added a comment. LGTM. Though I don't like the way that we need to loop `MxList` again when defining scheduling model, I think this can be a good practice to define RVV scheduling model in current TableGen's grammar. Comment

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-09 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:15 +class SiFive7IsWorstCaseMX MxList> { + string LLMUL = LargestLMUL.r; + bit c = !eq(mx, LLMUL); pcwang-thead wrote: > I think I have fixed the issue that `defar`

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-09 Thread Michael Maitland via Phabricator via cfe-commits
michaelmaitland updated this revision to Diff 520847. michaelmaitland marked an inline comment as done. michaelmaitland added a comment. Remove extra space before VLUpperBound. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-09 Thread Philip Reames via Phabricator via cfe-commits
reames accepted this revision. reames added a comment. This revision is now accepted and ready to land. LGTM, thought please wait for other review feedback to settle. I am very very happy to have this upstream, thank you! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-08 Thread Wang Pengcheng via Phabricator via cfe-commits
pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:15 +class SiFive7IsWorstCaseMX MxList> { + string LLMUL = LargestLMUL.r; + bit c = !eq(mx, LLMUL); I think I have fixed the issue that `defar` can't refer to template

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

2023-05-08 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:112 + // Note: c >= 1 since the smallest VLUpperBound is 512 / 8 = 8, and the + // largest division performed on VLUpperBound is in MF8 case with division + // by 8. Therefore, there