[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540949.
FreddyYe added a comment.

Remove #include 


Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rip], 123
+// CHECK:

[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Simon Pilgrim via Phabricator via cfe-commits 
RKSimon added inline comments.



Comment at: clang/lib/Headers/sm3intrin.h:21
+
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
+  __m128i __B,

Doxygen descriptions?



Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:4
+
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel 
--output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

FreddyYe wrote:
> pengfei wrote:
> > We can merge 64-bit tests into 32-bit ones. The same below.
> Due to these instructions support  rm form, hard to merge here?
I'd prefer to see 32/64 test coverage kept separate, but it'd be more useful 
for 64 to use xmm8-xmm15 and 64-specific gpr registers etc. to increase 
coverage.


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[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8331
+VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+  Sched<[WriteVecIMul]>;
+  }

skan wrote:
> Is the schedule appropriate?
I referred to SHA1MSG1's, any good ideas? I'll add a FIXME first here.



Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:4
+
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel 
--output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

pengfei wrote:
> We can merge 64-bit tests into 32-bit ones. The same below.
Due to these instructions support  rm form, hard to merge here?


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[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe updated this revision to Diff 540892.
FreddyYe marked 5 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK:  vsm3rnds2

[PATCH] D155147: Add SM3 instructions.

2023-07-13 Thread Kan Shengchen via Phabricator via cfe-commits 
skan added inline comments.



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8331
+VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+  Sched<[WriteVecIMul]>;
+  }

Is the schedule appropriate?



Comment at: llvm/test/MC/Disassembler/X86/sm3-32.txt:3
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown 
-x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s 
--check-prefixes=INTEL
+

Drop -x86-asm-syntax=intel


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[PATCH] D155147: Add SM3 instructions.

2023-07-13 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added inline comments.



Comment at: llvm/test/MC/Disassembler/X86/sm3-32.txt:1
+
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s 
--check-prefixes=ATT

Remove blank line



Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:1-2
+
+# isadb version: 6aa5c837365e1d1e6e53b3fc3d95ab184e9c06eb
+

Remove



Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:4
+
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel 
--output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

We can merge 64-bit tests into 32-bit ones. The same below.


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[PATCH] D155147: Add SM3 instructions.

2023-07-12 Thread Freddy, Ye via Phabricator via cfe-commits 
FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about these instructions, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


Repository:
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https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+//