[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji added inline comments.



Comment at: lib/Headers/ppc_wrappers/mmintrin.h:3
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal

jsji wrote:
> MaskRay wrote:
> > This is not Apache 2.
> Ah.. This was aligned with other headers .. but forgot to update to Apache 2.
> 
> @qiucf Please update it to Apache 2 as well. Thanks.
Updated to Apache 2 in https://reviews.llvm.org/rC359164


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[John McCall via Phabricator via cfe-commits]

rjmccall added a subscriber: chandlerc.
rjmccall added a comment.

@chandlerc, I hate to do this to you, but licensing question.


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji added a comment.

Thanks @MaskRay for help fixing and review!




Comment at: lib/Headers/ppc_wrappers/mmintrin.h:3
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal

MaskRay wrote:
> This is not Apache 2.
Ah.. This was aligned with other headers .. but forgot to update to Apache 2.

@qiucf Please update it to Apache 2 as well. Thanks.



Comment at: lib/Headers/ppc_wrappers/mmintrin.h:24
+
+/* Implemented from the specification included in the Intel C++ Compiler
+   User Guide and Reference, version 9.0.  */

MaskRay wrote:
> Is this considered a derivative work of the Intel C++ Compiler?
My understanding is that the `User Guide and Reference ` is the `specification` 
, implementation based on public specification should NOT be considered as 
`derivative` work. 

Otherwise, all codes that referenced `User Guide and Reference ` need to be 
considered derivative work?


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji added a comment.

In D59924#1475363 , @MaskRay wrote:

> May I ask why the mmintrin.h emulation layer must be added to the clang 
> resource directory? Why can't it be provided as a standalone library like 
> https://github.com/intel/ARM_NEON_2_x86_SSE ?


The intention is to lower the porting effort for users,  so that user don't 
need to modify their source or add their own additional headers wrapper layer.

> Will you add SSE/AVX/AVX512 emulation layer to the clang resource directory 
> as follow-ups?

Yes, more headers (eg: `xmmintrin.h`,  `emmintrin.h`) will follow.


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added inline comments.



Comment at: lib/Headers/ppc_wrappers/mmintrin.h:3
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal

This is not Apache 2.



Comment at: lib/Headers/ppc_wrappers/mmintrin.h:24
+
+/* Implemented from the specification included in the Intel C++ Compiler
+   User Guide and Reference, version 9.0.  */

Is this considered a derivative work of the Intel C++ Compiler?


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added a comment.

May I ask why the mmintrin.h emulation layer must be added to the clang 
resource directory? Why can't it be provided as a standalone library like 
https://github.com/intel/ARM_NEON_2_x86_SSE ? Will you add SSE/AVX/AVX512 
emulation layer to the clang resource directory as follow-ups?


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added a comment.

You use `%clang` (clang driver) because the test needs `-internal-isystem 
$resource_dir/include/ppc_wrappers`. A default release build of llvm sets 
`LLVM_ENABLE_ASSERTIONS` to off, the clang driver defaults to 
`-fdiscard-value-names`. This caused the test to break. I have fixed that in 
rC358953 .


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Phabricator via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC358949: [PowerPC] [Clang] Port MMX intrinsics and basic test 
cases to Power (authored by chaofan, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59924?vs=194446=196182#toc

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Files:
  lib/Driver/CMakeLists.txt
  lib/Driver/Driver.cpp
  lib/Driver/ToolChains/PPCLinux.cpp
  lib/Driver/ToolChains/PPCLinux.h
  lib/Headers/CMakeLists.txt
  lib/Headers/ppc_wrappers/mmintrin.h
  test/CodeGen/ppc-mmintrin.c
  test/Headers/ppc-intrinsics.c

Index: test/CodeGen/ppc-mmintrin.c
===
--- test/CodeGen/ppc-mmintrin.c
+++ test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,60 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: define available_externally i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG3]], align 8
+// CHECK: load i64, i64* [[REG4]], align 8
+// CHECK-BE: load i64, i64* [[REG3]], align 8
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK-NEXT: store <8 x i16> [[REG5]], <8 x i16>* [[REG6:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8]], align 16
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG7]], <8 x i16> [[REG9]])
+// CHECK-NEXT: store <16 x i8> [[REG10]], <16 x i8>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG12]], <8 x i16> [[REG13]])
+// CHECK-NEXT: store <16 x i8> [[REG14]], <16 x i8>* [[REG15:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG11]], align 16
+// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG15]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG16]], <16 x i8> zeroinitializer, <16 x i8> [[REG17]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi16(i64 [[REG18:[0-9a-zA-Z_%.]+]], i64 [[REG19:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG18]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG19]], i64* [[REG21:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG20]], align 8
+// CHECK: load i64, i64* [[REG21]], align 8
+// CHECK-BE: load i64, i64* [[REG20]], align 8
+// CHECK: [[REG22:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_packs(short vector[8], short vector[8])(<8 x i16> [[REG22]], <8 x i16> [[REG24]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi32(i64 [[REG25:[0-9a-zA-Z_%.]+]], i64 [[REG26:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG25]], i64* [[REG27:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG26]], i64* [[REG28:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG27]], align 8
+// CHECK: load i64, i64* [[REG28]], align 8
+// CHECK-BE: load i64, i64* [[REG27]], align 8
+// CHECK: [[REG29:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG30:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG30]], align 16
+// CHECK-NEXT: call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> [[REG29]], <4 x i32> [[REG31]])
Index: test/Headers/ppc-intrinsics.c
===
--- test/Headers/ppc-intrinsics.c
+++ 

[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji accepted this revision.
jsji added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for porting!


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Chaofan Qiu via Phabricator via cfe-commits]

qiucf marked an inline comment as done.
qiucf added a comment.

Part of a function signature can also match where it is called, so the test 
failed. I did the changes to pass the test but diff file was generated locally 
so it didn't contain this change. Sorry for the mistake.


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Chaofan Qiu via Phabricator via cfe-commits]

qiucf updated this revision to Diff 194446.
qiucf added a comment.

Fix error about a mismatch in mmintrin test cases.


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Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: not %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,60 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: define available_externally i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG3]], align 8
+// CHECK: load i64, i64* [[REG4]], align 8
+// CHECK-BE: load i64, i64* [[REG3]], align 8
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK-NEXT: store <8 x i16> [[REG5]], <8 x i16>* [[REG6:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8]], align 16
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG7]], <8 x i16> [[REG9]])
+// CHECK-NEXT: store <16 x i8> [[REG10]], <16 x i8>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG12]], <8 x i16> [[REG13]])
+// CHECK-NEXT: store <16 x i8> [[REG14]], <16 x i8>* [[REG15:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG11]], align 16
+// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG15]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG16]], <16 x i8> zeroinitializer, <16 x i8> [[REG17]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi16(i64 [[REG18:[0-9a-zA-Z_%.]+]], i64 [[REG19:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG18]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG19]], i64* [[REG21:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG20]], align 8
+// CHECK: load i64, i64* [[REG21]], align 8
+// CHECK-BE: load i64, i64* [[REG20]], align 8
+// CHECK: [[REG22:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_packs(short vector[8], short vector[8])(<8 x i16> [[REG22]], <8 x i16> [[REG24]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi32(i64 [[REG25:[0-9a-zA-Z_%.]+]], i64 [[REG26:[0-9a-zA-Z_%.]+]])
+// CHECK: store 

[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji requested changes to this revision.
jsji added a comment.
This revision now requires changes to proceed.

Please make sure you run all test before updating patch!




Comment at: clang/test/CodeGen/ppc-mmintrin.c:23
+// CHECK: i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 
[[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8

.../clang/test/CodeGen/ppc-mmintrin.c:23:11: error: CHECK: expected string not 
found in input
// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8


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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

[Chaofan Qiu via Phabricator via cfe-commits]

qiucf updated this revision to Diff 194253.
qiucf retitled this revision from "[PowerPC][Clang] Port MMX intrinsics and 
basic test cases to Power" to "[PowerPC] [Clang] Port MMX intrinsics and basic 
test cases to Power".
qiucf edited the summary of this revision.
qiucf added a comment.

- Add more check of mmintrin generated IR against endianness.
- Fix typo in PPCLinux header.
- Fix command error in ppc intrinsics header test.


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Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: not %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,60 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG3]], align 8
+// CHECK: load i64, i64* [[REG4]], align 8
+// CHECK-BE: load i64, i64* [[REG3]], align 8
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK-NEXT: store <8 x i16> [[REG5]], <8 x i16>* [[REG6:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8]], align 16
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG7]], <8 x i16> [[REG9]])
+// CHECK-NEXT: store <16 x i8> [[REG10]], <16 x i8>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG12]], <8 x i16> [[REG13]])
+// CHECK-NEXT: store <16 x i8> [[REG14]], <16 x i8>* [[REG15:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG11]], align 16
+// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG15]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG16]], <16 x i8> zeroinitializer, <16 x i8> [[REG17]])
+
+// CHECK: i64 @_mm_packs_pi16(i64 [[REG18:[0-9a-zA-Z_%.]+]], i64 [[REG19:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG18]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG19]], i64* [[REG21:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG20]], align 8
+// CHECK: load i64, i64* [[REG21]], align 8
+// CHECK-BE: load i64, i64* [[REG20]], align 8
+// CHECK: [[REG22:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23]], align 16

[PATCH] D59924: [PowerPC][Clang] Port MMX intrinsics and basic test cases to Power

[Chaofan Qiu via Phabricator via cfe-commits]

qiucf marked 2 inline comments as done.
qiucf added inline comments.



Comment at: clang/lib/Driver/ToolChains/PPCLinux.cpp:22
+  if (getArch() != llvm::Triple::ppc &&
+  !DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) &&
+  !DriverArgs.hasArg(options::OPT_nobuiltininc)) {

jsji wrote:
> Why we want to exclude these includes when `nostdinc` is on? These include 
> files are NOT standard include files.
> `-nostdinc`: Do not search the standard system directories or compiler 
> builtin directories for include files.
> From Clang's man page

And on Windows toolchain (MSVC.cpp), if turning on `-nostdinc`, Windows SDK 
files will also not be added into path.



Comment at: clang/test/Headers/ppc-intrinsics.c:7
+
+// RUN: NOT %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 
2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+

jsji wrote:
> NOT? 
> ` NOT: command not found ^`
It should be `not`, in downcase. This is what other test cases (see 
`test/CXX/temp/temp.spec/no-body.cpp`) use, to assert a non-zero exit code of a 
command. Otherwise, `llvm-lit` would complain and give a failure.


Repository:
  rC Clang

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https://reviews.llvm.org/D59924



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[PATCH] D59924: [PowerPC][Clang] Port MMX intrinsics and basic test cases to Power

[Jinsong Ji via Phabricator via cfe-commits]

jsji requested changes to this revision.
jsji added a comment.
This revision now requires changes to proceed.

Since we are adding new headers that is not originated by this patch, 
please also update the description (and commit message) to include who actually 
contributed to `mmintrin.h` and other headers.
eg:headers are mostly based on headers developed by Steven Munroe, with some 
contribution of Paul Clarke, Bill Schmidt,  Jinsong, Zeson.




Comment at: clang/lib/Driver/ToolChains/PPCLinux.cpp:22
+  if (getArch() != llvm::Triple::ppc &&
+  !DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) &&
+  !DriverArgs.hasArg(options::OPT_nobuiltininc)) {

Why we want to exclude these includes when `nostdinc` is on? These include 
files are NOT standard include files.



Comment at: clang/lib/Driver/ToolChains/PPCLinux.h:30
+} // end namespace toolchains
+} // namespace driver
+} // namespace clang

missing `end` in comment?



Comment at: clang/test/CodeGen/ppc-mmintrin.c:24
+// CHECK: [[REG1:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK: store <8 x i16> [[REG1]], <8 x i16>* [[REG2:[0-9a-zA-Z_%.]+]], align 
16
+// CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs

We should use `CHECK-NEXT` instead of `CHECK` here. This also apply to most of 
the following `CHECK`.



Comment at: clang/test/CodeGen/ppc-mmintrin.c:25
+// CHECK: store <8 x i16> [[REG1]], <8 x i16>* [[REG2:[0-9a-zA-Z_%.]+]], align 
16
+// CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs
+// CHECK: store <16 x i8> [[REG3]], <16 x i8>* [[REG4:[0-9a-zA-Z_%.]+]], align 
16

Why we omit checking two `load` for `vec_packs` here?



Comment at: clang/test/CodeGen/ppc-mmintrin.c:36
+// CHECK: i64 @_mm_packs_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: call <16 x i8> @vec_packs(short vector[8], short vector[8])
+

We should also check the `load` and make sure that the endian-specific code are 
working.



Comment at: clang/test/Headers/ppc-intrinsics.c:3
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -DTEST_MACRO -target 
powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target 
powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s

Why `-DTEST_MACRO`?



Comment at: clang/test/Headers/ppc-intrinsics.c:7
+
+// RUN: NOT %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 
2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+

NOT? 
` NOT: command not found ^`


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[PATCH] D59924: [PowerPC][Clang] Port MMX intrinsics and basic test cases to Power

[Chaofan Qiu via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: hfinkel, nemanjai, jsji, rsmith.
Herald added subscribers: cfe-commits, jdoerfert, kbarton, mgorny.
Herald added a project: clang.

This patch is for porting existing headers which include x86 intrinsics (MMX, 
SSE, SSE2, etc.) implementation to PowerPC platform (using Altivec).

Since x86 intrinsic headers (like mmintrin.h) are already at clang's header 
directory, I overrided PowerPC's toolchain class to insert new headers 
directory (named ppc_wrappers) into the path. This patch contains tests for 
several intrinsic functions. More complete tests will come in future patches.

To make this patch not too long, I only added mmintrin.h (MMX instruction set 
header).


Repository:
  rC Clang

https://reviews.llvm.org/D59924

Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -DTEST_MACRO -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: NOT %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,39 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: i64 @_mm_packs_pu16(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG1:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK: store <8 x i16> [[REG1]], <8 x i16>* [[REG2:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs
+// CHECK: store <16 x i8> [[REG3]], <16 x i8>* [[REG4:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG2]], align 16
+// CHECK: [[REG6:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG2]], align 16
+// CHECK: [[REG7:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG5]], <8 x i16> [[REG6]])
+// CHECK: store <16 x i8> [[REG7]], <16 x i8>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG9:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG4]], align 16
+// CHECK: [[REG10:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG8]], align 16
+// CHECK: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG9]], <16 x i8> zeroinitializer, <16 x i8> [[REG10]])
+
+// CHECK: i64 @_mm_packs_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: call <16 x i8> @vec_packs(short vector[8], short vector[8])
+
+// CHECK: i64 @_mm_packs_pi32(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: call <8 x i16> @vec_packs(int vector[4], int vector[4])
Index: clang/lib/Headers/ppc_wrappers/mmintrin.h
===
--- /dev/null
+++ clang/lib/Headers/ppc_wrappers/mmintrin.h
@@ -0,0 +1,1457 @@
+/*=== mmintrin.h - Implementation of MMX intrinsics on PowerPC -===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+