[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4657101 , @jrtc27 wrote: > In D70401#4657098 , @jrtc27 wrote: > >> GCC only ever defines __riscv_32e > > Hm, seems the comments about __riscv_32e were from months ago, ignore them

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

jrtc27 added a comment. In D70401#4657098 , @jrtc27 wrote: > GCC only ever defines __riscv_32e Hm, seems the comments about __riscv_32e were from months ago, ignore them if they aren't correct or have become outdated... Repository: rG LLVM Github

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

jrtc27 added a comment. GCC only ever defines __riscv_32e Comment at: clang/lib/Basic/Targets/RISCV.cpp:210 +if (Is64Bit) + Builder.defineMacro("__riscv_64e"); +else Ugh, these don't align with the normal pattern. __riscv_e already exists in the

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @craig.topper Thanks! @asb Hi Alex, I'd like to get another approval from you. Are there any more concerns? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___ cfe-commits mailing list

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

koute added a comment. Sorry for the comment spam, but could we please get this merged in finally? (: To people who hold the decision making power as to whether this is merged: are there still any blockers left, considering the consensus was to merge it? What's the hold up? Is there anything I

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. Thanks, I'll take another look. Rereading my previous comment I just wanted to clarify one part so it's not misunderstood. I said " I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4655408 , @asb wrote: > First of all, thank you to everyone who has been trying to nudge this forward > and apologies it must have been a frustrating experience. > > I appreciate there are users who want to see this and

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience. I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16200 SDValue Hi; - if (VA.getLocReg() == RISCV::X17) { // Second half of f64 is passed on the stack. This code has been rewritten recently. Please rebase

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. @asb @kito-cheng @jrtc27 @craig.topper Can I commit this since the support of RVE is really of great importance for some downstreams? If there are some problems, I will be there to fix them. If we all agree with this, I will mark RVE as exprimental and commit it then.

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu accepted this revision. zixuan-wu added a comment. This revision is now accepted and ready to land. LGTM if nobody objects. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

kekcheburec added a comment. In D70401#4653409 , @zixuan-wu wrote: > ping? Pong  Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added a comment. ping? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

luojia added a comment. In D70401#4635875 , @koute wrote: > I know that there are still open issues regarding the psABI, but considering > how slow it's been going, couldn't we merge this in anyway and mark it as > experimental and subject to change?

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper added inline comments. Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:479 + // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`, + // `unsigned long long` and `double` to have 4-bytes alignment. This + // behavior may be changed when

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added a comment. In D70401#4635875 , @koute wrote: > I know that there are still open issues regarding the psABI, but considering > how slow it's been going, couldn't we merge this in anyway and mark it as > experimental and subject to change?

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

koute added a comment. I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please? The patch is simple enough to not become a maintenance burden, and GCC

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:66 return CSR_XLEN_F32_Interrupt_SaveList; return CSR_Interrupt_SaveList; } Here also need adjust for rve. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

wangpc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:908 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ zixuan-wu wrote: > Hi, @wangpc

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:908 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ Hi, @wangpc it's hidden bug

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4411560 , @david-sawatzke wrote: > Thank you for the reply, I've compiled this with the most recent patch and > also didn't see a problem (but can't get it running with rustc). Building the > .ll with the older

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

david-sawatzke added a comment. Thank you for the reply, I've compiled this with the most recent patch and also didn't see a problem (but can't get it running with rustc). Building the .ll with the older patch, the same issue also occurs, so I *do* think its the old patch version? Here is the

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4409782 , @david-sawatzke wrote: > Hey I've tried using this patch (roughly following > https://noxim.xyz/blog/rust-ch32v003/). > > It uses the older version of this patch for the rust llvm version (here the >

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

david-sawatzke added a comment. Hey I've tried using this patch (roughly following https://noxim.xyz/blog/rust-ch32v003/). It uses the older version of this patch for the rust llvm version (here the llvm tree https://github.com/Noxime/llvm-project/tree/rv32e) and I use rust commit 0939ec13

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

kekcheburec added a comment. In D70401#4226597 , @pcwang-thead wrote: > In D70401#4226549 , @recallmenot > wrote: > >> In D70401#4205333 , @pcwang-thead >> wrote: >> >>>

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

pcwang-thead added a comment. In D70401#4226549 , @recallmenot wrote: > In D70401#4205333 , @pcwang-thead > wrote: > >> In D70401#4204511 , @recallmenot >> wrote: >> >>>

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

recallmenot added a comment. In D70401#4205333 , @pcwang-thead wrote: > In D70401#4204511 , @recallmenot > wrote: > >> Hi, I'm working on CH32V003 for rust and it uses RV32EC core. >> I tried replacing my distros