subject:"\[PATCH\] D92715\: \[Clang\]\[RISCV\] Define RISC\-V V builtin types"

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-02-18 Thread Hsiangkai Wang via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG766ee1096f0b: [Clang][RISCV] Define RISC-V V builtin types 
(authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-02-17 Thread Craig Topper via Phabricator via cfe-commits

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-02-09 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added a comment.

In D92715#2544233 , @craig.topper 
wrote:

> In D92715#2544178 , @HsiangKai wrote:
>
>> In D92715#2520925 , @craig.topper 
>> wrote:
>>
>>> I wonder if these types should be prefixed with "__clang_" like AArch64 
>>> tuple types?
>>
>> It seems only AArch64 tuple types have "__clang_" prefix.
>
> I think the other types don't have it because they are defined by an ARM 
> standard. See the description for https://reviews.llvm.org/D81721

It seems to use `__clang_` to differentiate tuple types and non-tuple types. 
The mangling rules are different between tuple types and non-tuple types in 
ARM. We have no mangling rules in our specification. I have a TODO item in this 
patch to clarify the mangling rules later.

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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-02-05 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

In D92715#2544178 , @HsiangKai wrote:

> In D92715#2520925 , @craig.topper 
> wrote:
>
>> I wonder if these types should be prefixed with "__clang_" like AArch64 
>> tuple types?
>
> It seems only AArch64 tuple types have "__clang_" prefix.

I think the other types don't have it because they are defined by an ARM 
standard. See the description for https://reviews.llvm.org/D81721


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-02-05 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added a comment.
Herald added subscribers: StephenFan, vkmr.

In D92715#2520925 , @craig.topper 
wrote:

> I wonder if these types should be prefixed with "__clang_" like AArch64 tuple 
> types?

It seems only AArch64 tuple types have "__clang_" prefix.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-25 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai updated this revision to Diff 319144.
HsiangKai added a comment.

Address @craig.topper's comments.


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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
---

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-25 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

I wonder if these types should be prefixed with "__clang_" like AArch64 tuple 
types?




Comment at: clang/lib/AST/ASTContext.cpp:3875
+IsFP)  
\
+  if (!EltTy->isBooleanType() &&   
\
+  ((EltTy->hasIntegerRepresentation() &&   
\

Should this be indented 2 more spaces? to align with the uin64_t above?



Comment at: clang/lib/AST/ASTContext.cpp:3882
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)  
\
+  if (EltTy->isBooleanType() && NumElts == NumEls) 
\
+return SingletonId;

Same here



Comment at: clang/lib/CodeGen/CGDebugInfo.cpp:784
+  // Mask type only occupies one vector register.
+  if (Info.ElementType == CGM.getContext().BoolTy) {
+Fractional = false;

Put this above the "if (FixedSize < 64)" and make that an "else if" so all 
assignments are in the same if/else structure.
You could pre-initialize Fractional to false and only assign it to true in the 
if/else chain.



Comment at: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c:1
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \

This seems to be dependent on the patch that adds the vadd builtins?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-19 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added a comment.

Ping. If we all agree to use builtin types to model RVV types, is there any 
other issues we need to address in this patch?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-19 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai updated this revision to Diff 316854.
HsiangKai added a comment.

According to "9. Vector Memory Alignment Constraints" in V specification, 
change the alignment of RVV types to the element size.


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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index:

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-14 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai updated this revision to Diff 316556.
HsiangKai added a comment.

Recover comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- /dev/null
+++

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-14 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai updated this revision to Diff 316553.
HsiangKai added a comment.

Refine debug info for RVV types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
---

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-14 Thread Liao Chunyu via Phabricator via cfe-commits

liaolucy added a comment.

In D92715#2495897 , @HsiangKai wrote:

> @liaolucy RISC-V vector types are sizeless types. Sizeless is kind of 
> characteristic for builtin types. If we use attribute to declare RISC-V 
> vector types, the frontend does not know anything about it. I still think to 
> define RISC-V vector types as builtin types is a better way.

Thanks, It's OK for me.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-13 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added a comment.

@liaolucy RISC-V vector types are sizeless types. Sizeless is kind of 
characteristic for builtin types. If we use attribute to declare RISC-V vector 
types, the frontend does not know anything about it. I still think to define 
RISC-V vector types as builtin types is a better way.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-08 Thread Erich Keane via Phabricator via cfe-commits

erichkeane added a comment.

In D92715#2446479 , @craig.topper 
wrote:

> I think it would be possible to add a new attribute to define these types. 
> But only specific values for parameters would be allowed so that it could 
> only generate the exact types we see here and the future segment load 
> patches. It wouldn't be general purpose like vector_size since the backend 
> design has a contract about how to translate the LMUL value from the scalable 
> type.
>
> This would introduce a new type in the AST or at least new subtype of 
> VectorType. This new type would need to be checked for in multiple places in 
> the compiler to define its behavior. As a datapoint 
> VectorType::SveFixedLengthDataVector appears 20 times. It's not clear that's 
> a reduction in complexity versus following what was already done with 
> AArch64SVEACLETypes.def. But I'm not a frontend expert.

FWIW, when I went to introduce the predecessor to _ExtInt, @rsmith was very 
against using an attribute spelling and wanted a declaration keyword (which is 
partly how _ExtInt ended up how it was).

I don't think it is controversial to be a new AST type however.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2021-01-05 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

Ping


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-28 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

@rsmith or @rjmccall do you have any opinions on whether we should use builtin 
types like SVE or create a new attribute for RISCV?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-10 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

I think it would be possible to add a new attribute to define these types. But 
only specific values for parameters would be allowed so that it could only 
generate the exact types we see here and the future segment load patches. It 
wouldn't be general purpose like vector_size since the backend design has a 
contract about how to translate the LMUL value from the scalable type.

This would introduce a new type in the AST or at least new subtype of 
VectorType. This new type would need to be checked for in multiple places in 
the compiler to define its behavior. As a datapoint 
VectorType::SveFixedLengthDataVector appears 20 times. It's not clear that's a 
reduction in complexity versus following what was already done with 
AArch64SVEACLETypes.def. But I'm not a frontend expert.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-10 Thread Alex Bradbury via Phabricator via cfe-commits

asb added a comment.

In D92715#2443376 , @craig.topper 
wrote:

> Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng  
> @khchen @liaolucy

I've added it to the agenda


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-09 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng  
@khchen @liaolucy


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-08 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

HsiangKai wrote:
> kito-cheng wrote:
> > khchen wrote:
> > > evandro wrote:
> > > > craig.topper wrote:
> > > > > craig.topper wrote:
> > > > > > jrtc27 wrote:
> > > > > > > liaolucy wrote:
> > > > > > > > RISC-V V has too many types, more than 200. All types use 
> > > > > > > > builtin types? Is it possible to reduce the number of builtin 
> > > > > > > > types?
> > > > > > > Indeed this is madness, what's wrong with just using 
> > > > > > > `__attribute__((vector_size(n)))` on the right type? We should 
> > > > > > > not be encouraging people to write code with 
> > > > > > > architecture-specific types... but if we _really_ need these 
> > > > > > > because RISC-V GCC decided this is how RISC-V V is going to look 
> > > > > > > them can we not just shove them all in a header as typedef's for 
> > > > > > > the architecture-independent attributed types and push that 
> > > > > > > complexity out of the compiler itself?
> > > > > > We are using  to specify types in IR. The size of 
> > > > > > the fixed part is being used to control the LMUL parameter. There 
> > > > > > is currently no way to spell a scalable vector type in C in a 
> > > > > > generic way.
> > > > > > 
> > > > > > Alternatively I guess we could make LMUL a parameter to the 
> > > > > > intrinsic and create the scalable IR types in the frontend based on 
> > > > > > it?
> > > > > I do wonder why we bothered to have signed and unsigned types. The 
> > > > > signedness of the operation should be carried in the intrinsic name.
> > > > Some integer operations distinguish between signed and unsigned.  
> > > > I do wonder why we bothered to have signed and unsigned types. The 
> > > > signedness of the operation should be carried in the intrinsic name.
> > > 
> > > I think the only good thing for supporting both signed and unsigned type 
> > > is that are more readable and compiler can does type checking for 
> > > programmer. 
> > > 
> > > maybe the alternative way is changing intrinsic naming rule like 
> > > 
> > > ```
> > > vint32m1_t a, b, c;
> > > a = vadd_i32m1(b, c);
> > > vuint32m1_t a, b, c;
> > > a = vadd_u32m1(b, c);
> > > vfloat32m1_t a, b, c;
> > > a = vadd_f32m1(b, c);
> > > ```
> > One quick thought about this, if the concern is too much built-in types are 
> > introduced in clang, maybe we could add a new attribute like 
> > `__attribute__((vector_size(n)))`, maybe named 
> > `__attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))`? and use 
> > that to define vector types like `typedef int 
> > __attribute__((riscv_scaleble_vector("2"))) vintm2_t`.
> To have signed and unsigned types, we could do type checking for the 
> builtins. For example, we have vmaxu_vv and vmax_vv. Users could pass signed 
> vector types into unsigned version vmaxu_vv if we only have types without 
> signed/unsigned. How could we tell users they pass values into the wrong 
> builtins?
Maybe I've been corrupted by X86 where there is just a single 128-bit integer 
vector type. Even though there are 8, 16, 32, 64 bit element operations with 
some being signed/unsigned.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-08 Thread Liao Chunyu via Phabricator via cfe-commits

liaolucy added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:68
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2_t", RvvInt8mf2, RvvInt8mf2Ty, 4,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1_t",  RvvInt8m1,  RvvInt8m1Ty,  8,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16, 8, 1, 
true)

eg: typedef __attribute__((riscv_vector_type(16/*EIBits*/, 1/*LMUL*/, ...)))  
int16_t vint16m1_t;
Please help to consider if this is feasible.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-08 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

kito-cheng wrote:
> khchen wrote:
> > evandro wrote:
> > > craig.topper wrote:
> > > > craig.topper wrote:
> > > > > jrtc27 wrote:
> > > > > > liaolucy wrote:
> > > > > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > > > > types? Is it possible to reduce the number of builtin types?
> > > > > > Indeed this is madness, what's wrong with just using 
> > > > > > `__attribute__((vector_size(n)))` on the right type? We should not 
> > > > > > be encouraging people to write code with architecture-specific 
> > > > > > types... but if we _really_ need these because RISC-V GCC decided 
> > > > > > this is how RISC-V V is going to look them can we not just shove 
> > > > > > them all in a header as typedef's for the architecture-independent 
> > > > > > attributed types and push that complexity out of the compiler 
> > > > > > itself?
> > > > > We are using  to specify types in IR. The size of 
> > > > > the fixed part is being used to control the LMUL parameter. There is 
> > > > > currently no way to spell a scalable vector type in C in a generic 
> > > > > way.
> > > > > 
> > > > > Alternatively I guess we could make LMUL a parameter to the intrinsic 
> > > > > and create the scalable IR types in the frontend based on it?
> > > > I do wonder why we bothered to have signed and unsigned types. The 
> > > > signedness of the operation should be carried in the intrinsic name.
> > > Some integer operations distinguish between signed and unsigned.  
> > > I do wonder why we bothered to have signed and unsigned types. The 
> > > signedness of the operation should be carried in the intrinsic name.
> > 
> > I think the only good thing for supporting both signed and unsigned type is 
> > that are more readable and compiler can does type checking for programmer. 
> > 
> > maybe the alternative way is changing intrinsic naming rule like 
> > 
> > ```
> > vint32m1_t a, b, c;
> > a = vadd_i32m1(b, c);
> > vuint32m1_t a, b, c;
> > a = vadd_u32m1(b, c);
> > vfloat32m1_t a, b, c;
> > a = vadd_f32m1(b, c);
> > ```
> One quick thought about this, if the concern is too much built-in types are 
> introduced in clang, maybe we could add a new attribute like 
> `__attribute__((vector_size(n)))`, maybe named 
> `__attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))`? and use that 
> to define vector types like `typedef int 
> __attribute__((riscv_scaleble_vector("2"))) vintm2_t`.
To have signed and unsigned types, we could do type checking for the builtins. 
For example, we have vmaxu_vv and vmax_vv. Users could pass signed vector types 
into unsigned version vmaxu_vv if we only have types without signed/unsigned. 
How could we tell users they pass values into the wrong builtins?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

khchen wrote:
> evandro wrote:
> > craig.topper wrote:
> > > craig.topper wrote:
> > > > jrtc27 wrote:
> > > > > liaolucy wrote:
> > > > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > > > types? Is it possible to reduce the number of builtin types?
> > > > > Indeed this is madness, what's wrong with just using 
> > > > > `__attribute__((vector_size(n)))` on the right type? We should not be 
> > > > > encouraging people to write code with architecture-specific types... 
> > > > > but if we _really_ need these because RISC-V GCC decided this is how 
> > > > > RISC-V V is going to look them can we not just shove them all in a 
> > > > > header as typedef's for the architecture-independent attributed types 
> > > > > and push that complexity out of the compiler itself?
> > > > We are using  to specify types in IR. The size of the 
> > > > fixed part is being used to control the LMUL parameter. There is 
> > > > currently no way to spell a scalable vector type in C in a generic way.
> > > > 
> > > > Alternatively I guess we could make LMUL a parameter to the intrinsic 
> > > > and create the scalable IR types in the frontend based on it?
> > > I do wonder why we bothered to have signed and unsigned types. The 
> > > signedness of the operation should be carried in the intrinsic name.
> > Some integer operations distinguish between signed and unsigned.  
> > I do wonder why we bothered to have signed and unsigned types. The 
> > signedness of the operation should be carried in the intrinsic name.
> 
> I think the only good thing for supporting both signed and unsigned type is 
> that are more readable and compiler can does type checking for programmer. 
> 
> maybe the alternative way is changing intrinsic naming rule like 
> 
> ```
> vint32m1_t a, b, c;
> a = vadd_i32m1(b, c);
> vuint32m1_t a, b, c;
> a = vadd_u32m1(b, c);
> vfloat32m1_t a, b, c;
> a = vadd_f32m1(b, c);
> ```
One quick thought about this, if the concern is too much built-in types are 
introduced in clang, maybe we could add a new attribute like 
`__attribute__((vector_size(n)))`, maybe named 
`__attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))`? and use that to 
define vector types like `typedef int 
__attribute__((riscv_scaleble_vector("2"))) vintm2_t`.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Kuan Hsu Chen (Zakk) via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

evandro wrote:
> craig.topper wrote:
> > craig.topper wrote:
> > > jrtc27 wrote:
> > > > liaolucy wrote:
> > > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > > types? Is it possible to reduce the number of builtin types?
> > > > Indeed this is madness, what's wrong with just using 
> > > > `__attribute__((vector_size(n)))` on the right type? We should not be 
> > > > encouraging people to write code with architecture-specific types... 
> > > > but if we _really_ need these because RISC-V GCC decided this is how 
> > > > RISC-V V is going to look them can we not just shove them all in a 
> > > > header as typedef's for the architecture-independent attributed types 
> > > > and push that complexity out of the compiler itself?
> > > We are using  to specify types in IR. The size of the 
> > > fixed part is being used to control the LMUL parameter. There is 
> > > currently no way to spell a scalable vector type in C in a generic way.
> > > 
> > > Alternatively I guess we could make LMUL a parameter to the intrinsic and 
> > > create the scalable IR types in the frontend based on it?
> > I do wonder why we bothered to have signed and unsigned types. The 
> > signedness of the operation should be carried in the intrinsic name.
> Some integer operations distinguish between signed and unsigned.  
> I do wonder why we bothered to have signed and unsigned types. The signedness 
> of the operation should be carried in the intrinsic name.

I think the only good thing for supporting both signed and unsigned type is 
that are more readable and compiler can does type checking for programmer. 

maybe the alternative way is changing intrinsic naming rule like 

```
vint32m1_t a, b, c;
a = vadd_i32m1(b, c);
vuint32m1_t a, b, c;
a = vadd_u32m1(b, c);
vfloat32m1_t a, b, c;
a = vadd_f32m1(b, c);
```


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Evandro Menezes via Phabricator via cfe-commits

evandro updated this revision to Diff 310044.
evandro marked 2 inline comments as done.

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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/lib/Serialization/ASTReader.cpp
===
--- clang/lib/Serialization/ASTReader.cpp
+++ clang/lib/Serialization/ASTReader.cpp
@@ -7030,6 +7030,11 @@
   T =

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Evandro Menezes via Phabricator via cfe-commits

evandro marked 7 inline comments as done.
evandro added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:32
+// - ElBits is the size of one element in bits (SEW).
+//
+// - IsSigned is true for vectors of signed integer elements and

HsiangKai wrote:
> craig.topper wrote:
> > NF argument isn't documented. And is always 1.
> > NF argument isn't documented. And is always 1.
> 
> We could remove it in this patch. The field will be needed when we are going 
> to upstream Zvlsseg implementation.
Perhaps we can just note that `NF` is going to be used by Zvlsseg instead.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

craig.topper wrote:
> craig.topper wrote:
> > jrtc27 wrote:
> > > liaolucy wrote:
> > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > types? Is it possible to reduce the number of builtin types?
> > > Indeed this is madness, what's wrong with just using 
> > > `__attribute__((vector_size(n)))` on the right type? We should not be 
> > > encouraging people to write code with architecture-specific types... but 
> > > if we _really_ need these because RISC-V GCC decided this is how RISC-V V 
> > > is going to look them can we not just shove them all in a header as 
> > > typedef's for the architecture-independent attributed types and push that 
> > > complexity out of the compiler itself?
> > We are using  to specify types in IR. The size of the 
> > fixed part is being used to control the LMUL parameter. There is currently 
> > no way to spell a scalable vector type in C in a generic way.
> > 
> > Alternatively I guess we could make LMUL a parameter to the intrinsic and 
> > create the scalable IR types in the frontend based on it?
> I do wonder why we bothered to have signed and unsigned types. The signedness 
> of the operation should be carried in the intrinsic name.
Some integer operations distinguish between signed and unsigned.  



Comment at: clang/lib/AST/ASTContext.cpp:2178
+  Width = 0; \
+  Align = 128; \
+  break;

HsiangKai wrote:
> craig.topper wrote:
> > Does this alignment need to be this high? The VMV0 register class in the 
> > backend has an alignment of 64 for spills. Just wondering why they aren't 
> > consistent.
> > Does this alignment need to be this high? The VMV0 register class in the 
> > backend has an alignment of 64 for spills. Just wondering why they aren't 
> > consistent.
> 
> Indeed, it should be 64.
> > Does this alignment need to be this high? The VMV0 register class in the 
> > backend has an alignment of 64 for spills. Just wondering why they aren't 
> > consistent.
> 
> Indeed, it should be 64.

Good catch!


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

craig.topper wrote:
> jrtc27 wrote:
> > liaolucy wrote:
> > > RISC-V V has too many types, more than 200. All types use builtin types? 
> > > Is it possible to reduce the number of builtin types?
> > Indeed this is madness, what's wrong with just using 
> > `__attribute__((vector_size(n)))` on the right type? We should not be 
> > encouraging people to write code with architecture-specific types... but if 
> > we _really_ need these because RISC-V GCC decided this is how RISC-V V is 
> > going to look them can we not just shove them all in a header as typedef's 
> > for the architecture-independent attributed types and push that complexity 
> > out of the compiler itself?
> We are using  to specify types in IR. The size of the fixed 
> part is being used to control the LMUL parameter. There is currently no way 
> to spell a scalable vector type in C in a generic way.
> 
> Alternatively I guess we could make LMUL a parameter to the intrinsic and 
> create the scalable IR types in the frontend based on it?
I do wonder why we bothered to have signed and unsigned types. The signedness 
of the operation should be carried in the intrinsic name.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

jrtc27 wrote:
> liaolucy wrote:
> > RISC-V V has too many types, more than 200. All types use builtin types? Is 
> > it possible to reduce the number of builtin types?
> Indeed this is madness, what's wrong with just using 
> `__attribute__((vector_size(n)))` on the right type? We should not be 
> encouraging people to write code with architecture-specific types... but if 
> we _really_ need these because RISC-V GCC decided this is how RISC-V V is 
> going to look them can we not just shove them all in a header as typedef's 
> for the architecture-independent attributed types and push that complexity 
> out of the compiler itself?
We are using  to specify types in IR. The size of the fixed 
part is being used to control the LMUL parameter. There is currently no way to 
spell a scalable vector type in C in a generic way.

Alternatively I guess we could make LMUL a parameter to the intrinsic and 
create the scalable IR types in the frontend based on it?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Jessica Clarke via Phabricator via cfe-commits

jrtc27 added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

liaolucy wrote:
> RISC-V V has too many types, more than 200. All types use builtin types? Is 
> it possible to reduce the number of builtin types?
Indeed this is madness, what's wrong with just using 
`__attribute__((vector_size(n)))` on the right type? We should not be 
encouraging people to write code with architecture-specific types... but if we 
_really_ need these because RISC-V GCC decided this is how RISC-V V is going to 
look them can we not just shove them all in a header as typedef's for the 
architecture-independent attributed types and push that complexity out of the 
compiler itself?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-07 Thread Liao Chunyu via Phabricator via cfe-commits

liaolucy added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

RISC-V V has too many types, more than 200. All types use builtin types? Is it 
possible to reduce the number of builtin types?


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-05 Thread Hsiangkai Wang via Phabricator via cfe-commits

HsiangKai added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:32
+// - ElBits is the size of one element in bits (SEW).
+//
+// - IsSigned is true for vectors of signed integer elements and

craig.topper wrote:
> NF argument isn't documented. And is always 1.
> NF argument isn't documented. And is always 1.

We could remove it in this patch. The field will be needed when we are going to 
upstream Zvlsseg implementation.



Comment at: clang/lib/AST/ASTContext.cpp:2178
+  Width = 0; \
+  Align = 128; \
+  break;

craig.topper wrote:
> Does this alignment need to be this high? The VMV0 register class in the 
> backend has an alignment of 64 for spills. Just wondering why they aren't 
> consistent.
> Does this alignment need to be this high? The VMV0 register class in the 
> backend has an alignment of 64 for spills. Just wondering why they aren't 
> consistent.

Indeed, it should be 64.



Comment at: clang/lib/CodeGen/CGDebugInfo.cpp:779
+
+  uint64_t Size = 0; // This is a scalable vector. See DwarfUnit.cpp:1414.
+  auto Align = getTypeAlignIfRequired(BT, CGM.getContext());

craig.topper wrote:
> Is there a function name in DwarfUnt.cpp that would be a better reference 
> here? Line numbers aren't stable.
> Is there a function name in DwarfUnt.cpp that would be a better reference 
> here? Line numbers aren't stable.

It should be `hasVectorBeenPadded()`. I have a downstream modification not 
upstreamed. We could remove the debug info for RVV types from this patch. I 
think it could be another patch for  debug info for scalable vector types.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-05 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:32
+// - ElBits is the size of one element in bits (SEW).
+//
+// - IsSigned is true for vectors of signed integer elements and

NF argument isn't documented. And is always 1.



Comment at: clang/include/clang/Basic/TargetInfo.h:221
 
+  unsigned HasRISCVVTypes : 1;
+

This needs to be initialized to false in TargetInfo::TargetInfo() in 
TargetInfo.cpp I think. And then set to true from lib/Basic/Targets/RISCV.cpp



Comment at: clang/lib/AST/ASTContext.cpp:2178
+  Width = 0; \
+  Align = 128; \
+  break;

Does this alignment need to be this high? The VMV0 register class in the 
backend has an alignment of 64 for spills. Just wondering why they aren't 
consistent.



Comment at: clang/lib/CodeGen/CGDebugInfo.cpp:779
+
+  uint64_t Size = 0; // This is a scalable vector. See DwarfUnit.cpp:1414.
+  auto Align = getTypeAlignIfRequired(BT, CGM.getContext());

Is there a function name in DwarfUnt.cpp that would be a better reference here? 
Line numbers aren't stable.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-05 Thread Evandro Menezes via Phabricator via cfe-commits

evandro updated this revision to Diff 309750.

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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/lib/Serialization/ASTReader.cpp
===
--- clang/lib/Serialization/ASTReader.cpp
+++ clang/lib/Serialization/ASTReader.cpp
@@ -7030,6 +7030,11 @@
   T = Context.Id##Ty; \
   break;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id,

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-05 Thread Evandro Menezes via Phabricator via cfe-commits

evandro updated this revision to Diff 309749.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}
Index: clang/lib/Serialization/ASTReader.cpp
===
--- clang/lib/Serialization/ASTReader.cpp
+++ clang/lib/Serialization/ASTReader.cpp
@@ -7030,6 +7030,11 @@
   T = Context.Id##Ty; \
   break;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id,

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-05 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added a comment.

Can you re-upload the patch with full context?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715

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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

2020-12-04 Thread Evandro Menezes via Phabricator via cfe-commits

evandro created this revision.
evandro added reviewers: Hsiang-Kai, craig.topper, rogfer01, frasercrmck.
Herald added subscribers: dexonsmith, NickHung, luismarques, apazos, 
sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, 
arphaman, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, martong, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, 
asb.
Herald added a reviewer: shafik.
evandro requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Add the types for the RISC-V V extension builtins.

Authored-by: Hsiangkai Wang 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92715

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/AST/TypeProperties.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/include/clang/module.modulemap
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/Sema/riscv-types.c
  clang/tools/libclang/CIndex.cpp

Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:| FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  //

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

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